User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 144 of 909 2019 Ambiq Micro, Inc.
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Control bit to enable/disable the PMU
3.8.2.30 TPIUCTRL Register
TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.
OFFSET: 0x00000250
INSTANCE 0 ADDRESS: 0x40020250
TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.
Table 187: PMUENABLE Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
ENABLE
Table 188: PMUENABLE Register Bits
Bit Name Reset RW Description
31:1 RSVD 0x0 RO
RESERVED.
0 ENABLE 0x1 RW
PMU Enable Control bit. When set, the MCU's PMU will place the MCU into
the lowest power consuming Deep Sleep mode upon execution of a WFI
instruction (dependent on the setting of the SLEEPDEEP bit in the ARM
SCR register). When cleared, regardless of the requested sleep mode, the
PMU will not enter the lowest power Deep Sleep mode, instead entering the
Sleep mode.
DIS = 0x0 - Disable MCU power management.
EN = 0x1 - Enable MCU power management.
Table 189: TPIUCTRL Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
CLKSEL
RSVD
ENABLE
Table 190: TPIUCTRL Register Bits
Bit Name Reset RW Description
31:11 RSVD 0x0 RO
RESERVED.