User Manual

Apollo3 Blue Datasheet

DS-A3-0p9p1 Page 14 of 909 2019 Ambiq Micro, Inc.

List of Tables

Table 1: Pin List and Function Table .......................................................................................... 49

Table 2: MCU Interrupt Assignments ........................................................................................ 70

Table 3: ARM Cortex-M4 Memory Map ................................................................................... 71

Table 4: MCU System Memory Map ......................................................................................... 71

Table 5: MCU Peripheral Device Memory Map ........................................................................ 72

Table 6: PWRCTRL Register Map ............................................................................................. 78

Table 7: SUPPLYSRC Register ................................................................................................. 79

Table 8: SUPPLYSRC Register Bits .......................................................................................... 79

Table 9: SUPPLYSTATUS Register .......................................................................................... 80

Table 10: SUPPLYSTATUS Register Bits ................................................................................ 80

Table 11: DEVPWREN Register ................................................................................................ 80

Table 12: DEVPWREN Register Bits ........................................................................................ 81

Table 13: MEMPWDINSLEEP Register ................................................................................... 82

Table 14: MEMPWDINSLEEP Register Bits ............................................................................ 82

Table 15: MEMPWREN Register .............................................................................................. 84

Table 16: MEMPWREN Register Bits ....................................................................................... 84

Table 17: MEMPWRSTATUS Register ..................................................................................... 85

Table 18: MEMPWRSTATUS Register Bits ............................................................................. 85

Table 19: DEVPWRSTATUS Register ...................................................................................... 86

Table 20: DEVPWRSTATUS Register Bits .............................................................................. 87

Table 21: SRAMCTRL Register ................................................................................................ 88

Table 22: SRAMCTRL Register Bits ......................................................................................... 88

Table 23: ADCSTATUS Register .............................................................................................. 89

Table 24: ADCSTATUS Register Bits ....................................................................................... 89

Table 25: MISC Register ............................................................................................................ 90

Table 26: MISC Register Bits ..................................................................................................... 90

Table 27: DEVPWREVENTEN Register ................................................................................... 91

Table 28: DEVPWREVENTEN Register Bits ........................................................................... 91

Table 29: MEMPWREVENTEN Register ................................................................................. 93

Table 30: MEMPWREVENTEN Register Bits .......................................................................... 93

Table 31: ITM Register Map ...................................................................................................... 95

Table 32: STIM0 Register .......................................................................................................... 97

Table 33: STIM0 Register Bits ................................................................................................... 97

Table 34: STIM1 Register .......................................................................................................... 97

Table 35: STIM1 Register Bits ................................................................................................... 97

Table 36: STIM2 Register .......................................................................................................... 98

Table 37: STIM2 Register Bits ................................................................................................... 98

Table 38: STIM3 Register .......................................................................................................... 98

Table 39: STIM3 Register Bits ................................................................................................... 98

Table 40: STIM4 Register .......................................................................................................... 99

Table 41: STIM4 Register Bits ................................................................................................... 99

Table 42: STIM5 Register .......................................................................................................... 99

Table 43: STIM5 Register Bits ................................................................................................... 99

Table 44: STIM6 Register ........................................................................................................ 100