User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 136 of 909 2019 Ambiq Micro, Inc.
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3.8.2.17 MISCCTRL Register
Miscellaneous control register.
OFFSET: 0x00000198
INSTANCE 0 ADDRESS: 0x40020198
Miscellaneous control register.
Table 162: XTALGENCTRL Register Bits
Bit Name Reset RW Description
31:14 RSVD 0x0 RO
RESERVED.
13:8
XTALKSBIAS-
TRIM
0x1 RW
XTAL IBIAS Kick start trim. This trim value is used during the startup pro-
cess to enable a faster lock.
7:2 XTALBIASTRIM 0x0 RW
XTAL BIAS trim
1:0 ACWARMUP 0x0 RW
Auto-calibration delay control
SEC1 = 0x0 - Warmup period of 1-2 seconds
SEC2 = 0x1 - Warmup period of 2-4 seconds
SEC4 = 0x2 - Warmup period of 4-8 seconds
SEC8 = 0x3 - Warmup period of 8-16 seconds
Table 163: MISCCTRL Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
BLE_RESETN
RESERVED_RW_0
Table 164: MISCCTRL Register Bits
Bit Name Reset RW Description
31:6 RSVD 0x0 RO
RESERVED.
5 BLE_RESETN 0x0 RW
BLE reset signal.
4:0
RESERVED_R-
W_0
0x0 RW
Reserved bits, always leave unchanged. The MISCCTRL register must be
modified via atomic RMW, leaving this bitfield completely unmodified. Fail-
ure to do so will result in unpredictable behavior.