User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 131 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
3.8.2.10 ADCPWRDLY Register
ADC Power Up Delay Control
OFFSET: 0x00000104
INSTANCE 0 ADDRESS: 0x40020104
ADC Power Up Delay Control
3.8.2.11 ADCCAL Register
ADC Calibration Control
OFFSET: 0x0000010C
INSTANCE 0 ADDRESS: 0x4002010C
ADC Calibration Control
Table 149: ADCPWRDLY Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD ADCPWR1 ADCPWR0
Table 150: ADCPWRDLY Register Bits
Bit Name Reset RW Description
31:16 RSVD 0x0 RO
RESERVED.
15:8 ADCPWR1 0x0 RW
ADC Reference Keeper enable delay in 16 ADC CLK increments for ADC_-
CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL = 0x2.
7:0 ADCPWR0 0x0 RW
ADC Reference Buffer Power Enable delay in 64 ADC CLK increments for
ADC_CLKSEL = 0x1, 32 ADC CLOCK increments for ADC_CLKSEL = 0x2.
Table 151: ADCCAL Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
ADCCALIBRATED
CALONPWRUP