User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 123 of 909 2019 Ambiq Micro, Inc.
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3.8.1 Register Memory Map
Table 130: MCUCTRL Register Map
Address(s) Register Name Description
0x40020000 CHIPPN Chip Information Register
0x40020004 CHIPID0 Unique Chip ID 0
0x40020008 CHIPID1 Unique Chip ID 1
0x4002000C CHIPREV Chip Revision
0x40020010 VENDORID Unique Vendor ID
0x40020014 SKU Unique Chip SKU
0x40020018 FEATUREENABLE Feature Enable on Burst and BLE
0x40020020 DEBUGGER Debugger Control
0x40020100 BODCTRL BOD control Register
0x40020104 ADCPWRDLY ADC Power Up Delay Control
0x4002010C ADCCAL ADC Calibration Control
0x40020110 ADCBATTLOAD ADC Battery Load Enable
0x40020118 ADCTRIM ADC Trims
0x4002011C ADCREFCOMP ADC Referece Keeper and Comparator Control
0x40020120 XTALCTRL XTAL Oscillator Control
0x40020124 XTALGENCTRL XTAL Oscillator General Control
0x40020198 MISCCTRL Miscellaneous control register.
0x400201A0 BOOTLOADER Bootloader and secure boot functions
0x400201A4 SHADOWVALID
Register to indicate whether the shadow regis-
ters have been successfully loaded from the
Flash Information Space.
0x400201B0 SCRATCH0 Scratch register that is not reset by any reset
0x400201B4 SCRATCH1 Scratch register that is not reset by any reset
0x400201C0 ICODEFAULTADDR
ICODE bus address which was present when a
bus fault occurred.
0x400201C4 DCODEFAULTADDR
DCODE bus address which was present when a
bus fault occurred.
0x400201C8 SYSFAULTADDR
System bus address which was present when a
bus fault occurred.
0x400201CC FAULTSTATUS
Reflects the status of the bus decoders' fault
detection. Any write to this register will clear all
of the status bits within the register.
0x400201D0 FAULTCAPTUREEN Enable the fault capture registers
0x40020200 DBGR1 Read-only debug register 1
0x40020204 DBGR2 Read-only debug register 2
0x40020220 PMUENABLE Control bit to enable/disable the PMU
0x40020250 TPIUCTRL
TPIU Control Register. Determines the clock
enable and frequency for the M4's TPIU inter-
face.