User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 12 of 909 2019 Ambiq Micro, Inc.
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Figure 45. Basic I2C Conditions ............................................................................................... 333
Figure 46. I2C Acknowledge .................................................................................................... 334
Figure 47. I2C 7-bit Address Operation ................................................................................... 334
Figure 48. I2C 10-bit Address Operation ................................................................................. 334
Figure 49. I2C Offset Address Transmission ........................................................................... 335
Figure 50. I2C Write Operation ................................................................................................ 335
Figure 51. I2C Read Operation ................................................................................................. 335
Figure 52. SPI Write Operation ................................................................................................ 336
Figure 53. SPI Read Operation ................................................................................................. 337
Figure 54. SPI CPOL and CPHA .............................................................................................. 337
Figure 55. Block Diagram for PDM Module ............................................................................ 357
Figure 56. Stereo PDM to PCM Conversion Path .................................................................... 358
Figure 57. PDM Clock Timing Diagram .................................................................................. 358
Figure 58. PDM Clock Source Switching Flow ....................................................................... 360
Figure 59. I2S Interface Data Format Timing .......................................................................... 363
Figure 60. I2S Interface Setup and Hold Timing Diagram ....................................................... 363
Figure 61. Block diagram for the General Purpose I/O (GPIO) Module .................................. 379
Figure 62. Pad Connection Details ........................................................................................... 388
Figure 63. Block diagram for the Clock Generator and Real Time Clock Module .................. 523
Figure 64. Apollo3 Blue Clock Tree ........................................................................................ 524
Figure 65. Block diagram for the Real Time Clock Module .................................................... 547
Figure 66. Block Diagram for One Counter/Timer Pair ........................................................... 557
Figure 67. Counter/Timer Operation, FN = 0 ........................................................................... 558
Figure 68. Counter/Timer Operation, FN = 1 ........................................................................... 559
Figure 69. Counter/Timer Operation, FN = 2 ........................................................................... 560
Figure 70. Counter/Timer Operation, FN = 3 ........................................................................... 560
Figure 71. Counter/Timer Operation, FN = 4 ........................................................................... 561
Figure 72. Counter/Timer Operation, FN = 5 ........................................................................... 562
Figure 73. Counter/Timer Operation, FN = 4 ........................................................................... 563
Figure 74. Counter/Timer Operation, FN = 7 ........................................................................... 563
Figure 75. Complex Operations with CMPR2 and CMPR3 ..................................................... 564
Figure 76. Dual Pattern Generation .......................................................................................... 565
Figure 77. Triggered One-Shot Patterns ................................................................................... 565
Figure 78. Terminated Repeat Patterns ..................................................................................... 566
Figure 79. Creating a Sine Wave .............................................................................................. 568
Figure 80. PWM-based Pulse Train .......................................................................................... 569
Figure 81. Pattern-based Pulse Train ........................................................................................ 569
Figure 82. CLR and EN Operation ........................................................................................... 570
Figure 83. CTIMER Interconnection ........................................................................................ 571
Figure 84. Block Diagram for the System Timer .................................................................... 669
Figure 85. Block diagram for the Watchdog Timer Module .................................................... 690
Figure 86. Block diagram for the Reset Generator Module ...................................................... 698
Figure 87. Block diagram of circuitry for Reset pin ................................................................. 699
Figure 88. Block Diagram for the UART Module .................................................................... 707
Figure 89. Block Diagram for ADC and Temperature Sensor ................................................. 723
Figure 90. Scan Flowchart ........................................................................................................ 733