User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 114 of 909 2019 Ambiq Micro, Inc.
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Trace Control Register.
Table 100: TCR Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
BUSY
ATB_ID RSVD
TS_FREQ
TS_PRESCALE
RSVD
SWV_ENABLE DWT_ENABLE
SYNC_ENABLE
TS_ENABLE
ITM_ENABLE
Table 101: TCR Register Bits
Bit Name Reset RW Description
31:24 RSVD 0x0 RO
RESERVED.
23 BUSY 0x0 RW
Set when ITM events present and being drained.
22:16 ATB_ID 0x0 RW
ATB ID for CoreSight system.
15:12 RSVD 0x0 RO
RESERVED.
11:10 TS_FREQ 0x0 RW
Global Timestamp Frequency.
9:8 TS_PRESCALE 0x0 RW
Timestamp prescaler: 0b00 = no prescaling 0b01 = divide by 4 0b10 =
divide by 16 0b11 = divide by 64.
7:5 RSVD 0x0 RO
RESERVED.
4 SWV_ENABLE 0x0 RW
Enable SWV behavior – count on TPIUEMIT and TPIUBAUD.
3 DWT_ENABLE 0x0 RW
Enables the DWT stimulus.
2 SYNC_ENABLE 0x0 RW
Enables sync packets for TPIU.
1 TS_ENABLE 0x0 RW
Enables differential timestamps. Differential timestamps are emitted when a
packet is written to the FIFO with a non-zero timestamp counter, and when
the timestamp counter overflows. Timestamps are emitted during idle times
after a fixed number of cycles. This provides a time reference for packets
and inter-packet gaps.
0 ITM_ENABLE 0x0 RW
Enable ITM. This is the master enable, and must be set before ITM Stimulus
and Trace Enable registers can be written.