User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 11 of 909 2019 Ambiq Micro, Inc.
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List of Figures
Figure 1. Apollo3 Blue MCU BGA Pin Configuration Diagram ............................................... 47
Figure 2. Apollo3 Blue MCU CSP Pin Configuration Diagram - Top View ............................. 48
Figure 3. Block Diagram for the Ultra-Low Power Apollo3 Blue MCU ................................... 66
Figure 4. ARM Cortex-M4 Vector Table for Apollo3 Blue MCU ............................................. 69
Figure 5. Block Diagram for Flash and OTP Memory Subsystem ........................................... 155
Figure 6. Block Diagram for Apollo3 Blue MCU with Flash Cache ....................................... 157
Figure 7. Block diagram for the Flash Memory Controller ...................................................... 170
Figure 8. Block diagram for the SRAM Interface .................................................................... 171
Figure 9. Secure Boot Flow ...................................................................................................... 173
Figure 10. Secure OTA Flow .................................................................................................... 174
Figure 11. Block Diagram for the BLE Module ....................................................................... 178
Figure 12. Block Diagram for the MSPI Master Module ......................................................... 216
Figure 13. MSPI Interface Diagram ......................................................................................... 227
Figure 14. Block Diagram for the I2C/SPI Master Module ..................................................... 258
Figure 15. Clocking Structure for IOM Module ....................................................................... 260
Figure 16. IO_CLK Generation ................................................................................................ 261
Figure 17. Direct Mode 5-byte Write Transfer ......................................................................... 263
Figure 18. Direct Mode 5-byte Read ........................................................................................ 263
Figure 19. Register Write Data Fetches ................................................................................... 265
Figure 20. IOM Pause Example ............................................................................................... 266
Figure 21. CQ Pause Bit Fetching ............................................................................................ 267
Figure 22. I2C/SPI Master Clock Generation ........................................................................... 269
Figure 23. Basic I2C Conditions ............................................................................................... 270
Figure 24. I2C Acknowledge .................................................................................................... 271
Figure 25. I2C 7-bit Address Operation ................................................................................... 272
Figure 26. I2C 10-bit Address Operation ................................................................................. 272
Figure 27. I2C Offset Address Transmission ........................................................................... 272
Figure 28. I2C Normal Write Operation ................................................................................... 273
Figure 29. I2C Normal Read Operation .................................................................................... 273
Figure 30. I2C Raw Write Operation ........................................................................................ 273
Figure 31. I2C Raw Read Operation ........................................................................................ 274
Figure 32. SPI Normal Write Operation ................................................................................... 275
Figure 33. SPI Normal Read Operation .................................................................................... 276
Figure 34. SPI Raw Write Operation ........................................................................................ 276
Figure 35. SPI Raw Read Operation ......................................................................................... 276
Figure 36. SPI Combined Operation ......................................................................................... 277
Figure 37. SPI CPOL and CPHA .............................................................................................. 278
Figure 38. Flow Control at Beginning of a Write Transfer ...................................................... 280
Figure 39. Flow Control at Beginning of a Raw Read Transfer ............................................... 280
Figure 40. Flow Control in the Middle of a Write Transfer ..................................................... 281
Figure 41. Flow Control in the Middle of a Read Transfer ...................................................... 281
Figure 42. Block diagram for the I2C/SPI Slave Module ......................................................... 325
Figure 43. I2C/SPI Slave Module LRAM Addressing ............................................................. 326
Figure 44. I2C/SPI Slave Module FIFO ................................................................................... 330