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Apollo3 Blue Datasheet

DS-A3-0p9p1 Page 1 of 912 2019 Ambiq Micro, Inc.

Apollo3 Blue Datasheet

Doc. ID: DS-A3-0p9p1

Revision 0.9.1

Feb 2019

IMPORTANT NOTICE:

This datasheet includes content which is accurate to the

extent possible, but is preliminary and certain content may

not be fully validated.

Summary of content (909 pages)

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Apollo3 Blue Datasheet Apollo3 Blue Datasheet Doc. ID: DS-A3-0p9p1 Revision 0.9.1 Feb 2019 IMPORTANT NOTICE: This datasheet includes content which is accurate to the extent possible, but is preliminary and certain content may not be fully validated. DS-A3-0p9p1 Page 1 of 912 2019 Ambiq Micro, Inc. All rights reserved.
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Apollo3 Blue Datasheet Ultra-Low Power MCU Family Compact package option: - 3.37 x 3.25 mm(<0.35mm thk pkg) 66-pin CSP with 37 GPIO - 5 x 5 mm (<0.5mm thk pkg) 81-pin BGA with 50 GPIO Features Ultra-low supply current: - 6 µA/MHz executing from flash at 3.3 V - 6 µA/MHz executing from RAM at 3.3 V - 1 µA deep sleep mode (BLE Off) with RTC at 3.
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Apollo3 Blue Datasheet Table of Content 1. Apollo3 Blue MCU Package Pins ..................................................................................... 47 1.1 Pin Configuration ....................................................................................................... 47 1.2 Pin Connections ......................................................................................................... 48 2. System Core ............................................................................
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Apollo3 Blue Datasheet 6.1.2 Main Features ................................................................................................. 178 6.2 Functional Description ............................................................................................. 179 6.2.1 Data Transfers ................................................................................................. 179 6.3 BLEIF Registers ..................................................................................................
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Apollo3 Blue Datasheet 8.7.2 Start Data Transfer .......................................................................................... 271 8.7.3 Stop Data Transfer .......................................................................................... 271 8.7.4 Data Valid ....................................................................................................... 271 8.7.5 Acknowledge ..................................................................................................
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Apollo3 Blue Datasheet 9.9.6 Address Operation .......................................................................................... 334 9.9.7 Offset Address Transmission .......................................................................... 334 9.9.8 Write Operation .............................................................................................. 335 9.9.9 Read Operation ............................................................................................... 335 9.9.
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Apollo3 Blue Datasheet 11.5 Module-specific Pad Configuration ....................................................................... 389 11.5.1 Implementing IO Master Connections .......................................................... 389 11.5.2 MSPI Connection .......................................................................................... 396 11.5.3 Implementing IO Slave Connections ............................................................ 396 11.5.
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Apollo3 Blue Datasheet 13.1 Functional Overview .............................................................................................. 557 13.2 Counter/Timer Functions ....................................................................................... 558 13.2.1 Single Count (FN = 0) .................................................................................. 558 13.2.2 Repeated Count (FN = 1) .............................................................................. 559 13.2.
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Apollo3 Blue Datasheet 15. Watchdog Timer Module ............................................................................................... 690 15.1 Functional Overview .............................................................................................. 690 15.2 WDT Registers ...................................................................................................... 690 15.2.1 Register Memory Map ..................................................................................
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Apollo3 Blue Datasheet 19.2.1 Register Memory Map .................................................................................. 765 19.2.2 VCOMP Registers ........................................................................................ 766 20. Voltage Regulator Module ............................................................................................. 771 20.1 Functional Overview .............................................................................................. 771 20.
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Apollo3 Blue Datasheet List of Figures Figure 1. Apollo3 Blue MCU BGA Pin Configuration Diagram ............................................... 47 Figure 2. Apollo3 Blue MCU CSP Pin Configuration Diagram - Top View ............................. 48 Figure 3. Block Diagram for the Ultra-Low Power Apollo3 Blue MCU ................................... 66 Figure 4. ARM Cortex-M4 Vector Table for Apollo3 Blue MCU ............................................. 69 Figure 5.
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Apollo3 Blue Datasheet Figure 45. Basic I2C Conditions ............................................................................................... 333 Figure 46. I2C Acknowledge .................................................................................................... 334 Figure 47. I2C 7-bit Address Operation ................................................................................... 334 Figure 48. I2C 10-bit Address Operation .........................................................
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Apollo3 Blue Datasheet Figure 91. Switchable Battery Load ......................................................................................... 736 Figure 92. Block diagram for the Voltage Comparator Module ............................................... 764 Figure 93. Block Diagram for the Voltage Regulator Module ................................................. 771 Figure 94. BLE/Burst Buck Ton Adjustment Diagram ............................................................ 773 Figure 95.
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Apollo3 Blue Datasheet List of Tables Table 1: Pin List and Function Table .......................................................................................... 49 Table 2: MCU Interrupt Assignments ........................................................................................ 70 Table 3: ARM Cortex-M4 Memory Map ................................................................................... 71 Table 4: MCU System Memory Map ...............................................................
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Apollo3 Blue Datasheet Table 45: STIM6 Register Bits ................................................................................................. 100 Table 46: STIM7 Register ........................................................................................................ 100 Table 47: STIM7 Register Bits ................................................................................................. 100 Table 48: STIM8 Register .................................................................
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Apollo3 Blue Datasheet Table 91: STIM29 Register Bits ............................................................................................... 111 Table 92: STIM30 Register ...................................................................................................... 112 Table 93: STIM30 Register Bits ............................................................................................... 112 Table 94: STIM31 Register ...................................................................
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Apollo3 Blue Datasheet Table 137: CHIPREV Register ................................................................................................. 127 Table 138: CHIPREV Register Bits ......................................................................................... 127 Table 139: VENDORID Register ............................................................................................. 127 Table 140: VENDORID Register Bits ......................................................................
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Apollo3 Blue Datasheet Table 183: DBGR1 Register ..................................................................................................... 143 Table 184: DBGR1 Register Bits ............................................................................................. 143 Table 185: DBGR2 Register ..................................................................................................... 143 Table 186: DBGR2 Register Bits ................................................................
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Apollo3 Blue Datasheet Table 229: NCR0END Register Bits ........................................................................................ 164 Table 230: NCR1START Register ........................................................................................... 165 Table 231: NCR1START Register Bits .................................................................................... 165 Table 232: NCR1END Register ....................................................................................
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Apollo3 Blue Datasheet Table 275: INTEN Register ...................................................................................................... 191 Table 276: INTEN Register Bits .............................................................................................. 192 Table 277: INTSTAT Register ................................................................................................. 193 Table 278: INTSTAT Register Bits ..............................................................
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Apollo3 Blue Datasheet Table 321: BLEDBG Register .................................................................................................. 215 Table 322: BLEDBG Register Bits .......................................................................................... 215 Table 323: Command Queue Example ..................................................................................... 222 Table 324: CQFLAGS .........................................................................................
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Apollo3 Blue Datasheet Table 367: DMASTAT Register Bits ....................................................................................... 247 Table 368: DMATARGADDR Register .................................................................................. 248 Table 369: DMATARGADDR Register Bits ........................................................................... 248 Table 370: DMADEVADDR Register .....................................................................................
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Apollo3 Blue Datasheet Table 413: INTSTAT Register Bits .......................................................................................... 295 Table 414: INTCLR Register ................................................................................................... 297 Table 415: INTCLR Register Bits ............................................................................................ 297 Table 416: INTSET Register .........................................................................
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Apollo3 Blue Datasheet Table 459: STATUS Register Bits ........................................................................................... 319 Table 460: MSPICFG Register ................................................................................................. 320 Table 461: MSPICFG Register Bits ......................................................................................... 320 Table 462: MI2CCFG Register ...........................................................................
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Apollo3 Blue Datasheet Table 504: REGACCINTCLR Register Bits ............................................................................ 351 Table 505: REGACCINTSET Register .................................................................................... 351 Table 506: REGACCINTSET Register Bits ............................................................................ 352 Table 507: HOST_IER Register ...............................................................................................
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Apollo3 Blue Datasheet Table 550: DMACFG Register ................................................................................................. 376 Table 551: DMACFG Register Bits ......................................................................................... 376 Table 552: DMATOTCOUNT Register ................................................................................... 377 Table 553: DMATOTCOUNT Register Bits ............................................................................
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Apollo3 Blue Datasheet Table 596: UART1 RTS Configuration .................................................................................... 403 Table 597: UART1 CTS Configuration .................................................................................... 403 Table 599: PDM DATA Configuration .................................................................................... 404 Table 600: I2S BCLK Configuration ...................................................................................
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Apollo3 Blue Datasheet Table 642: PADREGI Register Bits ......................................................................................... 437 Table 643: PADREGJ Register ................................................................................................ 439 Table 644: PADREGJ Register Bits ......................................................................................... 439 Table 645: PADREGK Register .............................................................................
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Apollo3 Blue Datasheet Table 688: ENSA Register Bits ................................................................................................ 482 Table 689: ENSB Register ........................................................................................................ 483 Table 690: ENSB Register Bits ................................................................................................ 483 Table 691: ENCA Register ...................................................................
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Apollo3 Blue Datasheet Table 734: ALTPADCFGK Register Bits ................................................................................ 503 Table 735: ALTPADCFGL Register ........................................................................................ 504 Table 736: ALTPADCFGL Register Bits ................................................................................ 504 Table 737: ALTPADCFGM Register .......................................................................................
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Apollo3 Blue Datasheet Table 780: CLOCKEN2STAT Register ................................................................................... 539 Table 781: CLOCKEN2STAT Register Bits ............................................................................ 540 Table 782: CLOCKEN3STAT Register ................................................................................... 540 Table 783: CLOCKEN3STAT Register Bits ............................................................................
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Apollo3 Blue Datasheet Table 826: CMPRB0 Register Bits ........................................................................................... 581 Table 827: CTRL0 Register ...................................................................................................... 582 Table 828: CTRL0 Register Bits .............................................................................................. 582 Table 829: CMPRAUXA0 Register ...................................................................
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Apollo3 Blue Datasheet Table 872: CMPRAUXA3 Register Bits .................................................................................. 612 Table 873: CMPRAUXB3 Register ......................................................................................... 612 Table 874: CMPRAUXB3 Register Bits .................................................................................. 612 Table 875: AUX3 Register ...............................................................................................
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Apollo3 Blue Datasheet Table 918: AUX6 Register Bits ................................................................................................ 639 Table 919: TMR7 Register ....................................................................................................... 641 Table 920: TMR7 Register Bits ................................................................................................ 641 Table 921: CMPRA7 Register ..................................................................
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Apollo3 Blue Datasheet Table 964: SCMPR2 Register ................................................................................................... 676 Table 965: SCMPR2 Register Bits ........................................................................................... 677 Table 966: SCMPR3 Register ................................................................................................... 677 Table 967: SCMPR3 Register Bits ..................................................................
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Apollo3 Blue Datasheet Table 1010: INTEN Register Bits ............................................................................................ 695 Table 1011: INTSTAT Register ............................................................................................... 695 Table 1012: INTSTAT Register Bits ........................................................................................ 695 Table 1013: INTCLR Register ...........................................................................
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Apollo3 Blue Datasheet Table 1056: IER Register Bits .................................................................................................. 718 Table 1057: IES Register .......................................................................................................... 719 Table 1058: IES Register Bits .................................................................................................. 719 Table 1059: MIS Register .............................................................
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Apollo3 Blue Datasheet Table 1102: FIFO Register ....................................................................................................... 754 Table 1103: FIFO Register Bits ................................................................................................ 754 Table 1104: FIFOPR Register .................................................................................................. 754 Table 1105: FIFOPR Register Bits ..........................................................
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Apollo3 Blue Datasheet Table 1148: BLE Crystal Oscillator ......................................................................................... 778 Table 1149: Analog to Digital Converter (ADC) ..................................................................... 779 Table 1150: SIMO Buck Converter .......................................................................................... 783 Table 1151: BLE Buck Converter .................................................................................
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Apollo3 Blue Datasheet Table 1194: SECURITYWIREDIFCCFG5 Register ............................................................... 819 Table 1195: SECURITYWIREDIFCCFG5 Register Bits ........................................................ 819 Table 1196: SECURITYVERSION Register ........................................................................... 820 Table 1197: SECURITYVERSION Register Bits ....................................................................
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Apollo3 Blue Datasheet Table 1240: CUSTKEKW5 Register ........................................................................................ 831 Table 1241: CUSTKEKW5 Register Bits ................................................................................ 831 Table 1242: CUSTKEKW6 Register ........................................................................................ 831 Table 1243: CUSTKEKW6 Register Bits ................................................................................
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Apollo3 Blue Datasheet Table 1286: CUSTKEKW28 Register ...................................................................................... 842 Table 1287: CUSTKEKW28 Register Bits .............................................................................. 843 Table 1288: CUSTKEKW29 Register ...................................................................................... 843 Table 1289: CUSTKEKW29 Register Bits ..............................................................................
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Apollo3 Blue Datasheet Table 1332: CUSTAUTHW19 Register ................................................................................... 854 Table 1333: CUSTAUTHW19 Register Bits ........................................................................... 854 Table 1334: CUSTAUTHW20 Register ................................................................................... 854 Table 1335: CUSTAUTHW20 Register Bits ...........................................................................
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Apollo3 Blue Datasheet Table 1378: CUSTPUBKEYW10 Register .............................................................................. 865 Table 1379: CUSTPUBKEYW10 Register Bits ...................................................................... 866 Table 1380: CUSTPUBKEYW11 Register .............................................................................. 866 Table 1381: CUSTPUBKEYW11 Register Bits ......................................................................
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Apollo3 Blue Datasheet Table 1424: CUSTPUBKEYW33 Register .............................................................................. 877 Table 1425: CUSTPUBKEYW33 Register Bits ...................................................................... 877 Table 1426: CUSTPUBKEYW34 Register .............................................................................. 877 Table 1427: CUSTPUBKEYW34 Register Bits ......................................................................
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Apollo3 Blue Datasheet Table 1470: CUSTPUBKEYW56 Register .............................................................................. 888 Table 1471: CUSTPUBKEYW56 Register Bits ...................................................................... 889 Table 1472: CUSTPUBKEYW57 Register .............................................................................. 889 Table 1473: CUSTPUBKEYW57 Register Bits ......................................................................
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Apollo3 Blue Datasheet 1. Apollo3 Blue MCU Package Pins 1.1 Pin Configuration Figure 1. Apollo3 Blue MCU BGA Pin Configuration Diagram DS-A3-0p9p1 Page 47 of 909 2019 Ambiq Micro, Inc. All rights reserved.
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Apollo3 Blue Datasheet Figure 2. Apollo3 Blue MCU CSP Pin Configuration Diagram - Top View 1.2 Pin Connections The following table lists the external pins of the Apollo3 Blue MCU and their available functions. DS-A3-0p9p1 Page 48 of 909 2019 Ambiq Micro, Inc. All rights reserved.
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Apollo3 Blue Datasheet Table 1: Pin List and Function Table BGA Pin Number CSP Pin Number GPIO Pad Number Function Select Number Pad Function Name Description Pin Type POWER B2 B8 - - VDDP VDD Supply for SIMO Buck Converter Power B1 B9 - - VDDB VDD Supply for BLE/Burst Buck Converter Power F3 F5 - - VDDH VDD Supply for I/O Pads Power C4 C5 - - VDDA Analog Voltage Supply Power RF Voltage Supply Power High Voltage Digital Supply Power RF Voltage Supply Power J4 H6 -
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Apollo3 Blue Datasheet Table 1: Pin List and Function Table BGA Pin Number CSP Pin Number GPIO Pad Number Function Select Number Pad Function Name G3 G6 - - RSTN External Reset Input Input/ Output J2 H8 - - RFIOM RF I/O Negative Analog J1 H9 - - RFIOP RF I/O Positive Analog J3 - - - TXEN Transmitter Enable Output 0 SLSCL I2C Slave Clock Input 1 SLSCK SPI Slave Clock Input 2 CLKOUT Programmable Output Clock Output 3 GPIO00 General Purpose I/O Input/ Output 4
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Apollo3 Blue Datasheet Table 1: Pin List and Function Table BGA Pin Number G5 D9 E9 DS-A3-0p9p1 CSP Pin Number F4 C1 D2 GPIO Pad Number 3 4 5 Function Select Number Pad Function Name 0 UA0RTS 1 SLnCE SPI Slave Chip Enable 2 NCE3 IO Master N Chip Select 3 Table 564, “NCE Encoding Table,” on page 382 Output 3 GPIO03 General Purpose I/O Input/ Output 4 RSV 5 MSPI7 MSPI Master Interface Signal 7 See “MSPI Connection” on page 393.
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Apollo3 Blue Datasheet Table 1: Pin List and Function Table BGA Pin Number E8 F9 F8 DS-A3-0p9p1 CSP Pin Number E2 F2 D1 GPIO Pad Number 6 7 8 Function Select Number Pad Function Name 0 M0SDAWIR3 1 M0MISO SPI Master 0 Input Data Input 2 UA0CTS UART0 Clear To Send (CTS) Input 3 GPIO06 General Purpose I/O 4 RSV Reserved 5 CT10 Timer/Counter Interface Signal 10 See “Implementing Counter/Timer Connections” on page 394.
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Apollo3 Blue Datasheet Table 1: Pin List and Function Table BGA Pin Number G7 G8 B5 DS-A3-0p9p1 CSP Pin Number F1 E1 E4 GPIO Pad Number 9 10 11 Function Select Number Pad Function Name 0 M1SDAWIR3 1 M1MISO 2 NCE9 3 Description Pin Type Bidirectional Open Drain I2C Master 1 Data SPI Master 1 3 Wire Data SPI Master 1 Input Data Input IO Master N Chip Select 9 Table 564, “NCE Encoding Table,” on page 382 Output GPIO09 General Purpose I/O Input/ Output 4 SCCIO Secure Card Contr
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Apollo3 Blue Datasheet Table 1: Pin List and Function Table BGA Pin Number A7 B7 D7 DS-A3-0p9p1 CSP Pin Number B4 B3 A3 GPIO Pad Number Function Select Number Pad Function Name Description Pin Type 0 ADCD0NSE9 Analog to Digital Converter Differential N Input 0 / Single-Ended Input 9 Input 1 NCE12 2 CT0 3 IO Master N Chip Select 12 Table 564, “NCE Encoding Table,” on page 382 Output Timer/Counter Interface Signal 0 See “Implementing Counter/Timer Connections” on page 397.
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Apollo3 Blue Datasheet Table 1: Pin List and Function Table BGA Pin Number C7 D4 D3 C5 DS-A3-0p9p1 CSP Pin Number C3 A5 D4 E5 GPIO Pad Number 15 16 17 18 Function Select Number Pad Function Name 0 ADCD1N Analog to Digital Converter Differential N Input 1 Input 1 NCE15 IO Master N Chip Select 15 Table 564, “NCE Encoding Table,” on page 382 Output 2 UART1RX 3 GPIO15 4 PDMDATA PDM Data 5 RSV Reserved 6 SWDIO Description Pin Type UART1 Receive Input Input/ Output Gener
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Apollo3 Blue Datasheet Table 1: Pin List and Function Table BGA Pin Number C3 G6 F7 DS-A3-0p9p1 CSP Pin Number E6 C2 C4 GPIO Pad Number 19 20 21 Function Select Number Pad Function Name 0 CMPRF0 1 NCE19 2 CT6 3 Description Pin Type Comparator Reference 0 Input IO Master N Chip Select 19 Table 564, “NCE Encoding Table,” on page 382 Output Timer/Counter Interface Signal 6 See “Implementing Counter/Timer Connections” on page 394.
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Apollo3 Blue Datasheet Table 1: Pin List and Function Table BGA Pin Number C9 D8 C8 DS-A3-0p9p1 CSP Pin Number A1 B1 B2 GPIO Pad Number 22 23 24 Function Select Number Pad Function Name 0 UART0TX 1 NCE22 2 CT12 3 Description Pin Type UART0 Transmit Output IO Master N Chip Select 22 Table 564, “NCE Encoding Table,” on page 382 Output Timer/Counter Interface Signal 12 See “Implementing Counter/Timer Connections” on page 397.
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Apollo3 Blue Datasheet Table 1: Pin List and Function Table BGA Pin Number A8 B8 B9 DS-A3-0p9p1 CSP Pin Number D3 A2 E3 GPIO Pad Number 25 26 27 Function Select Number Pad Function Name 0 UART1RX 1 NCE25 2 CT1 3 GPIO25 4 M2SDAWIR3 5 M2MISO 6 RSV Reserved 7 RSV Reserved 0 RSV Reserved 1 NCE26 2 CT3 3 Description Pin Type UART1 Receive Input IO Master N Chip Select 25 Table 564, “NCE Encoding Table,” on page 382 Output Timer/Counter Interface Signal 1 See “Imple
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Apollo3 Blue Datasheet Table 1: Pin List and Function Table BGA Pin Number A9 A5 F6 DS-A3-0p9p1 CSP Pin Number F3 B5 - GPIO Pad Number 28 29 30 Function Select Number Pad Function Name 0 I2SWCLK 1 NCE28 2 CT7 3 GPIO28 4 RSV 5 M2MOSI 6 UART0TX 7 RSV 0 ADCSE1 1 NCE29 2 CT9 3 Description Pin Type I2S Word Clock Input IO Master N Chip Select 28 Table 564, “NCE Encoding Table,” on page 382 Output Timer/Counter Interface Signal 7 See “Implementing Counter/Timer Connect
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Apollo3 Blue Datasheet Table 1: Pin List and Function Table BGA Pin Number D5 E6 B6 DS-A3-0p9p1 CSP Pin Number - - - GPIO Pad Number 31 32 33 Function Select Number Pad Function Name 0 ADCSE3 1 NCE31 2 CT13 3 GPIO31 4 UART0RX UART0 Receive 5 SCCCLK Secure Card Controller Clock Output 6 BLEIF_MISO BLE Interface MISO Observation Output 7 UA1RTS UART1 Request To Send (RTS) Output 0 ADCSE4 Analog to Digital Converter Single-Ended Input 4 1 NCE32 2 CT15 3 Descriptio
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Apollo3 Blue Datasheet Table 1: Pin List and Function Table BGA Pin Number C6 D6 H6 H7 DS-A3-0p9p1 CSP Pin Number - - - - GPIO Pad Number 34 35 36 37 Function Select Number Pad Function Name 0 ADCSE6 1 NCE34 2 Description Pin Type Analog to Digital Converter Single-Ended Input 6 Input IO Master N Chip Select 34 Table 564, “NCE Encoding Table,” on page 382 Output UA1RTS UART1 Request To Send (RTS) Output 3 GPIO34 General Purpose I/O Input/ Output 4 CMPRF2 Voltage Compar
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Apollo3 Blue Datasheet Table 1: Pin List and Function Table BGA Pin Number J6 J8 J9 E5 DS-A3-0p9p1 CSP Pin Number - H2 H1 H3 GPIO Pad Number 38 39 Function Select Number Pad Function Name 0 TRIG3 ADC Trigger Input 3 1 NCE38 IO Master N Chip Select 38 Table 564, “NCE Encoding Table,” on page 382 2 UA0CTS UART0 Clear To Send (CTS) 3 GPIO38 General Purpose I/O 4 RSV 5 M3MOSI 6 UART1RX Pin Type Input Output Input Input/ Output Reserved SPI Master 3 Output Data Output UART1
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Apollo3 Blue Datasheet Table 1: Pin List and Function Table BGA Pin Number H5 J5 J7 DS-A3-0p9p1 CSP Pin Number - - H4 GPIO Pad Number 42 43 44 Function Select Number Pad Function Name 0 UART1TX 1 NCE42 2 CT16 3 Description Pin Type UART1 Transmit Output IO Master N Chip Select 42 Table 564, “NCE Encoding Table,” on page 382 Output See “Implementing Counter/Timer Connections” on page 397.
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Apollo3 Blue Datasheet Table 1: Pin List and Function Table BGA Pin Number F5 E7 H9 DS-A3-0p9p1 CSP Pin Number - - G2 GPIO Pad Number 45 46 47 Function Select Number Pad Function Name 0 UA1CTS 1 NCE45 2 CT22 3 Description Pin Type UART1 Clear To Send (CTS) Input IO Master N Chip Select 45 Table 564, “NCE Encoding Table,” on page 382 Output Timer/Counter Interface Signal 22 See “Implementing Counter/Timer Connections” on page 394.
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Apollo3 Blue Datasheet Table 1: Pin List and Function Table BGA Pin Number G9 H8 DS-A3-0p9p1 CSP Pin Number G3 G1 GPIO Pad Number 48 49 Function Select Number Pad Function Name 0 UART0TX 1 NCE48 2 CT28 3 Description Pin Type UART0 Transmit Output IO Master N Chip Select 48 Table 564, “NCE Encoding Table,” on page 382 Output Timer/Counter Interface Signal 28 See “Implementing Counter/Timer Connections” on page 394.
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Apollo3 Blue Datasheet 2. System Core MCU Cortex M4 with FPU, Up to 96MHz 16kB Flash Cache Wake-Up Interrupt Controller Power Management Unit Sys Timer / RTC LFRC HFRC Timers / PWM (x8) XTAL Stepper Motor BTLE Sensor Peripherals 1MB Flash BTLE 5 Controller 14b, 1.2MS/s, 15-Channel ADC Security Low Leakage Comparator BTLE Radio Temp Sensor 384kB RAM Reset Controller ...
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Apollo3 Blue Datasheet The Apollo3 Blue MCU provides support for higher performance operating modes through Ambiq’s TurboSPOT technology. The TurboSPOT technology allows applications to meet critical timing as/when needed while still providing extremely high energy efficiency operation. The Apollo3 Blue MCU also supports secure boot using Ambiq’s SecureSPOT technology enabling applications to establish and maintain a root of trust from boot to execution.
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Apollo3 Blue Datasheet 3. MCU Core Details At the center of the Apollo3 Blue MCU is a 32-bit ARM Cortex-M4 core with the floating point option. This 3-stage pipeline implementation of the ARM v7-M architecture offers highly efficient processing in a very low power design. The ARM M DAP enables debugging access via a Serial Wire Interface from outside of the MCU which allows access to all of the memory and peripheral devices of the MCU.
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Apollo3 Blue Datasheet Exception Number IRQ Number 255 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 . 17 . . 16 . 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 239 Offset 0x03FC . . . 2 1 0 -1 -2 -5 0x00C0 0x00BC 0x009C 0x0098 0x0094 0x0090 0x008C 0x0088 0x0084 0x0080 0x007C 0x0078 0x0074 0x0070 0x006C 0x0068 0x0064 0x0060 0x005C 0x0058 0x0054 0x0050 0x004C 0x0048 0x0044 0x0040 0x003C 0x0038 0x002C Vector Peripheral/Description IRQ239 . . .
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Apollo3 Blue Datasheet The Cortex-M4 allows the user to assign various interrupts to different priority levels based on the requirements of the application. In this MCU implementation, 8 different priority levels are available. One additional feature of the M4 interrupt architecture is the ability to relocate the Vector Table to a different address. This could be useful if the application requires a different set of interrupt service routines for a particular mode of an application.
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Apollo3 Blue Datasheet 3.2 Memory Map ARM has a well-defined memory map for devices based on the ARM v7-M Architecture. The M4 further refines this map in the area of the Peripheral and System address ranges.
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Apollo3 Blue Datasheet Table 5 shows the address mapping for the peripheral devices of the Base Platform.
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Apollo3 Blue Datasheet Table 5: MCU Peripheral Device Memory Map Address Device 0x50007000 – 0x50007FFF I2C / SPI Master3 0x50008000 – 0x50008FFF I2C / SPI Master4 0x50009000 – 0x50009FFF I2C / SPI Master5 0x5000A000 – 0x5000BFFF Reserved 0x5000C000 – 0x5000CFFF BLE 0x5000D000 – 0x5000FFFF Reserved 0x50010000 – 0x500103FF ADC 0x50010400 – 0x50010FFF Reserved 0x50011000 – 0x500113FF PDM 0x50011400 – 0x50013FFF Reserved 0x50014000 – 0x500143FF MSPI Master 0x50014400 – 0x5001FFFF Rese
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Apollo3 Blue Datasheet You can use the MPU to: ▪ Enforce privilege rules. ▪ Separate processes. ▪ Enforce access rules. 3.4 System Busses The ARM Cortex-M4 utilizes 3 instances of the AMBA AHB bus for communication with memory and peripherals. The ICode bus is designed for instruction fetches from the ‘Code’ memory space while the DCode bus is designed for data and debug accesses in that same region. The System bus is designed for fetches to the SRAM and other peripheral devices of the MCU.
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Apollo3 Blue Datasheet will be wrong when using Burst Mode. It is recommended not to use SYSTICK and Burst Mode together unless proper compensation is made. 3.5.1.2 Active Mode In the Active Mode, the M4 is powered up, clocks are active, and instructions are being executed. In this mode, the M4 expects all (enabled) devices attached to the AHB and APB to be powered and clocked for normal access. All of the non-debug ARM clocks (FCLK, HCLK) are active in this state.
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Apollo3 Blue Datasheet 3.5.2.3 SYS Sleep Mode 0 (SS0) In SYS Sleep Mode 0, this is a low power state for the MCU. In this mode, all SRAM memory is retained (up to 384KB), Flash memory is in standby, HFRC is on, main core clock domain is gated but peripheral clock domains can be on. CPU is in Sleep Mode.
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Apollo3 Blue Datasheet ▪ ▪ ▪ ▪ ▪ ▪ 384KB: SDS1-384RET 256KB: SDS1-256RET 128KB: SDS1-128RET 64KB: SDS1-64RET 8KB: SDS1-8RET 0KB: SDS1 3.5.2.7 SYS Deep Sleep Mode 2 (SDS2) In SYS Deep Sleep Mode 2, this is the minimum power state that the MCU can resume normal operation.
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Apollo3 Blue Datasheet status register. The power controller also supports event notification to indicate peripheral power transition completion. Event notification is the preferred power-optimized method in lieu of status polling. The power controller is also the primary control block for the BLE/Burst and SIMO Buck converters as well as the LDO regulators when Bucks are disabled.
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Apollo3 Blue Datasheet 3.5.3.1.2 PWRCTRL Registers 3.5.3.1.2.1SUPPLYSRC Register Voltage Regulator Select Register OFFSET: 0x00000000 INSTANCE 0 ADDRESS: 0x40021000 This register controls the enable for BLE BUCK.
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Apollo3 Blue Datasheet 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 RSVD 0 1 0 0 BLEBUCKON 3 1 SIMOBUCKON Table 9: SUPPLYSTATUS Register Table 10: SUPPLYSTATUS Register Bits Bit Name Reset RW 31:2 RSVD 0x0 RO Description RESERVED. Indicates whether the BLE (if supported) domain and burst (if supported) domain is supplied from the LDO or the Buck.
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Apollo3 Blue Datasheet Table 12: DEVPWREN Register Bits Bit Name Reset RW 31:14 RSVD 0x0 RO Description RESERVED.
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Apollo3 Blue Datasheet Table 12: DEVPWREN Register Bits Bit Name Reset RW Description Power up IO Master 0 1 PWRIOM0 0x0 RW EN = 0x1 - Power up IO Master 0 DIS = 0x0 - Power down IO Master 0 Power up IO Slave 0 PWRIOS 0x0 RW EN = 0x1 - Power up IO slave DIS = 0x0 - Power down IO slave 3.5.3.1.2.4MEMPWDINSLEEP Register Powerdown SRAM banks in Deep Sleep mode OFFSET: 0x0000000C INSTANCE 0 ADDRESS: 0x4002100C This controls the power down of the SRAM banks in deep sleep mode.
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Apollo3 Blue Datasheet Table 14: MEMPWDINSLEEP Register Bits Bit Name 13 FLASH0PWDSLP Reset RW Description Powerdown flash0 in deep sleep 0x1 RW EN = 0x1 - Flash0 is powered down during deepsleep DIS = 0x0 - Flash0 is kept powered on during deepsleep Selects which SRAM banks are powered down in deep sleep mode, causing the contents of the bank to be lost.
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Apollo3 Blue Datasheet CACHEB0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 RSVD 1 4 1 3 FLASH0 3 0 FLASH1 3 1 CACHEB2 Table 15: MEMPWREN Register 1 2 1 1 1 0 0 9 0 8 0 7 SRAM 0 6 0 5 0 4 0 3 0 2 0 1 0 0 DTCM Table 16: MEMPWREN Register Bits Bit 31 Name CACHEB2 Reset 0x1 RW RW Description Power up Cache Bank 2. This works in conjunction with Cache enable from flash_cache module.
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Apollo3 Blue Datasheet Table 16: MEMPWREN Register Bits Bit Name Reset RW Description Power up DTCM 2:0 DTCM 0x7 RW NONE = 0x0 - Do not enable power to any DTCMs GROUP0DTCM0 = 0x1 - Power ON only GROUP0_DTCM0 GROUP0DTCM1 = 0x2 - Power ON only GROUP0_DTCM1 GROUP0 = 0x3 - Power ON only DTCMs in group0 GROUP1 = 0x4 - Power ON only DTCMs in group1 ALL = 0x7 - Power ON all DTCMs 3.5.3.1.2.
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Apollo3 Blue Datasheet Table 18: MEMPWRSTATUS Register Bits Bit Name Reset RW 10 SRAM7 0x1 RO 9 SRAM6 0x1 RO 8 SRAM5 0x1 RO 7 SRAM4 0x1 RO 6 SRAM3 0x1 RO 5 SRAM2 0x1 RO 4 SRAM1 0x1 RO 3 SRAM0 0x1 RO 2 DTCM1 0x1 RO 1 DTCM01 0x1 RO 0 DTCM00 0x1 RO Description This bit is 1 if power is supplied to SRAM GROUP7 This bit is 1 if power is supplied to SRAM GROUP6 This bit is 1 if power is supplied to SRAM GROUP5 This bit is 1 if power is supplied to SRAM GROUP4 This
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Apollo3 Blue Datasheet Table 20: DEVPWRSTATUS Register Bits Bit Name Reset RW Description 31 SYSDEEPSLEEP 0x0 RO This bit is 1 if SYSTEM has been in Deep Sleep. Write '1' to this bit to clear it.
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Apollo3 Blue Datasheet 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 RSVD 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 SRAMLIGHTSLEEP 0 5 RSVD 0 4 0 3 0 2 0 1 0 0 RSVD 3 0 SRAMCLKGATE 3 1 SRAMMASTERCLKGATE Table 21: SRAMCTRL Register Table 22: SRAMCTRL Register Bits Bit Name Reset RW 31:20 RSVD 0x0 RO SRAMLIGHTSLEEP 19:8 0x0 RW Description This bitfield is reserved for future use. Light Sleep enable for each TCM/SRAM bank.
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Apollo3 Blue Datasheet 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 RSVD 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BGTPWD 2 7 ADCPWD 2 8 VBATPWD 2 9 VPTATPWD 3 0 REFKEEPPWD 3 1 REFBUFPWD Table 23: ADCSTATUS Register Table 24: ADCSTATUS Register Bits Bit Name Reset RW 31:6 RSVD 0x0 RO 5 REFBUFPWD 0x1 RO 4 REFKEEPPWD 0x1 RO 3 VBATPWD 0x1 RO 2 VPTATPWD 0x1 RO 1 BGTPWD 0x1 RO 0 ADCPWD 0x1 RO Description RESERVED.
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Apollo3 Blue Datasheet 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 RSVD 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 SIMOBUCKEN 2 6 FORCECOREVRLPPDM 2 7 FORCEMEMVRLPTIMERS 2 8 FORCECOREVRLPTIMERS 2 9 FORCEMEMVRADC 3 0 MEMVRLPBLE 3 1 FORCEBLEBUCKACT Table 25: MISC Register Table 26: MISC Register Bits Bit Name Reset RW 31:8 RSVD 0x0 RO 7 FORCEBLEBUCKACT 0x0 RW Description RESERVED.
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Apollo3 Blue Datasheet Table 26: MISC Register Bits Bit Name Reset RW Description Enables and Selects the SIMO Buck as the supply for the low-voltage power domain. It takes the initial value from the bit set in Customer INFO space. 0 SIMOBUCKEN 0x0 RW EN = 0x1 - Enable the SIMO Buck DIS = 0x0 - Disable the SIMO Buck 3.5.3.1.2.11DEVPWREVENTEN Register Event enable register to control which DEVPWRSTATUS bits are routed to event input of CPU.
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Apollo3 Blue Datasheet Table 28: DEVPWREVENTEN Register Bits Bit Name Reset RW Description Control BLE power-on status event 8 BLELEVEN 0x0 RW EN = 0x1 - Enable BLE power-on status event DIS = 0x0 - Disable BLE power-on status event Control PDM power-on status event 7 PDMEVEN 0x0 RW EN = 0x1 - Enable PDM power-on status event DIS = 0x0 - Disable PDM power-on status event Control MSPI power-on status event 6 MSPIEVEN 0x0 RW EN = 0x1 - Enable MSPI power-on status event DIS = 0x0 - Disable
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Apollo3 Blue Datasheet 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 RSVD 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 SRAMEN 0 5 0 4 0 3 0 2 0 1 0 0 DTCMEN CACHEB0EN 2 9 FLASH0EN 3 0 FLASH1EN 3 1 CACHEB2EN Table 29: MEMPWREVENTEN Register Table 30: MEMPWREVENTEN Register Bits Bit Name Reset RW 31 CACHEB2EN 0x0 RW Description Control CACHEB2 power-on status event EN = 0x1 - Enable CACHE BANK 2 status event DIS = 0x0 - Disable CACHE BANK 2 status event Control
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Apollo3 Blue Datasheet Table 30: MEMPWREVENTEN Register Bits Bit Name Reset RW Description Enable DTCM power-on status event 2:0 DTCMEN 0x0 RW NONE = 0x0 - Do not enable DTCM power-on status event GROUP0DTCM0EN = 0x1 - Enable GROUP0_DTCM0 power on status event GROUP0DTCM1EN = 0x2 - Enable GROUP0_DTCM1 power on status event GROUP0EN = 0x3 - Enable DTCMs in group0 power on status event GROUP1EN = 0x4 - Enable DTCMs in group1 power on status event ALL = 0x7 - Enable all DTCM power on status event 3.
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Apollo3 Blue Datasheet 3.7.
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Apollo3 Blue Datasheet Table 31: ITM Register Map Address(s) Register Name Description 0xE0000FB4 LOCKSREG Lock Status Register 0xE0000FD0 PID4 Peripheral Identification Register 4 0xE0000FD4 PID5 Peripheral Identification Register 5 0xE0000FD8 PID6 Peripheral Identification Register 6 0xE0000FDC PID7 Peripheral Identification Register 7 0xE0000FE0 PID0 Peripheral Identification Register 0 0xE0000FE4 PID1 Peripheral Identification Register 1 0xE0000FE8 PID2 Peripheral Identificati
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Apollo3 Blue Datasheet 3.7.2 ITM Registers 3.7.2.1 STIM0 Register Stimulus Port Register 0 OFFSET: 0x00000000 INSTANCE 0 ADDRESS: 0xE0000000 Stimulus Port Register 0 Table 32: STIM0 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 STIM0 Table 33: STIM0 Register Bits Bit Name Reset RW 31:0 STIM0 0x0 RW 3.7.2.
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Apollo3 Blue Datasheet 3.7.2.3 STIM2 Register Stimulus Port Register 2 OFFSET: 0x00000008 INSTANCE 0 ADDRESS: 0xE0000008 Stimulus Port Register 2 Table 36: STIM2 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 STIM2 Table 37: STIM2 Register Bits Bit Name Reset RW 31:0 STIM2 0x0 RW 3.7.2.4 Description Stimulus Port Register 2.
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Apollo3 Blue Datasheet Stimulus Port Register 4 Table 40: STIM4 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 STIM4 Table 41: STIM4 Register Bits Bit Name Reset RW 31:0 STIM4 0x0 RW 3.7.2.6 Description Stimulus Port Register 4.
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Apollo3 Blue Datasheet Table 44: STIM6 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 STIM6 Table 45: STIM6 Register Bits Bit Name Reset RW 31:0 STIM6 0x0 RW 3.7.2.8 Description Stimulus Port Register 6.
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Apollo3 Blue Datasheet Table 48: STIM8 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 STIM8 Table 49: STIM8 Register Bits Bit Name Reset RW 31:0 STIM8 0x0 RW Description Stimulus Port Register 8. 3.7.2.
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Apollo3 Blue Datasheet Table 52: STIM10 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 STIM10 Table 53: STIM10 Register Bits Bit Name Reset RW 31:0 STIM10 0x0 RW Description Stimulus Port Register 10. 3.7.2.
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Apollo3 Blue Datasheet Table 56: STIM12 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 STIM12 Table 57: STIM12 Register Bits Bit Name Reset RW 31:0 STIM12 0x0 RW Description Stimulus Port Register 12. 3.7.2.
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Apollo3 Blue Datasheet Table 60: STIM14 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 STIM14 Table 61: STIM14 Register Bits Bit Name Reset RW 31:0 STIM14 0x0 RW Description Stimulus Port Register 14. 3.7.2.
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Apollo3 Blue Datasheet Table 64: STIM16 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 STIM16 Table 65: STIM16 Register Bits Bit Name Reset RW 31:0 STIM16 0x0 RW Description Stimulus Port Register 16. 3.7.2.
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Apollo3 Blue Datasheet Table 68: STIM18 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 STIM18 Table 69: STIM18 Register Bits Bit Name Reset RW 31:0 STIM18 0x0 RW Description Stimulus Port Register 18. 3.7.2.
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Apollo3 Blue Datasheet Table 72: STIM20 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 STIM20 Table 73: STIM20 Register Bits Bit Name Reset RW 31:0 STIM20 0x0 RW Description Stimulus Port Register 20. 3.7.2.
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Apollo3 Blue Datasheet Table 76: STIM22 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 STIM22 Table 77: STIM22 Register Bits Bit Name Reset RW 31:0 STIM22 0x0 RW Description Stimulus Port Register 22. 3.7.2.
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Apollo3 Blue Datasheet Table 80: STIM24 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 STIM24 Table 81: STIM24 Register Bits Bit Name Reset RW 31:0 STIM24 0x0 RW Description Stimulus Port Register 24. 3.7.2.
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Apollo3 Blue Datasheet Table 84: STIM26 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 STIM26 Table 85: STIM26 Register Bits Bit Name Reset RW 31:0 STIM26 0x0 RW Description Stimulus Port Register 26. 3.7.2.
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Apollo3 Blue Datasheet Table 88: STIM28 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 STIM28 Table 89: STIM28 Register Bits Bit Name Reset RW 31:0 STIM28 0x0 RW Description Stimulus Port Register 28. 3.7.2.
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Apollo3 Blue Datasheet Table 92: STIM30 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 STIM30 Table 93: STIM30 Register Bits Bit Name Reset RW 31:0 STIM30 0x0 RW Description Stimulus Port Register 30. 3.7.2.
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Apollo3 Blue Datasheet Table 96: TER Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 STIMENA Table 97: TER Register Bits Bit Name Reset RW 31:0 STIMENA 0x0 RW Description Bit mask to enable tracing on ITM stimulus ports. One bit per stimulus port.. 3.7.2.34 TPR Register Trace Privilege Register. OFFSET: 0x00000E40 INSTANCE 0 ADDRESS: 0xE0000E40 Trace Privilege Register.
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Apollo3 Blue Datasheet Trace Control Register.
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Apollo3 Blue Datasheet 3.7.2.
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Apollo3 Blue Datasheet Table 105: LOCKSREG Register Bits Bit Name Reset RW Description 1 ACCESS 0x0 RO Write access to component is blocked. All writes are ignored, reads are permitted. 0 PRESENT 0x1 RO Indicates that a lock mechanism exists for this component. 3.7.2.
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Apollo3 Blue Datasheet Table 109: PID5 Register Bits Bit Name Reset RW 31:0 PID5 0x0 R0 Description Peripheral Identification 5. 3.7.2.
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Apollo3 Blue Datasheet Table 113: PID7 Register Bits Bit Name Reset RW 31:0 PID7 0x0 R0 Description Peripheral Identification 7. 3.7.2.
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Apollo3 Blue Datasheet Table 117: PID1 Register Bits Bit Name Reset RW 31:0 PID1 0xb0 R0 Description Peripheral Identification 1. 3.7.2.
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Apollo3 Blue Datasheet Table 121: PID3 Register Bits Bit Name Reset RW 31:0 PID3 0x0 R0 Description Peripheral Identification 3. 3.7.2.
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Apollo3 Blue Datasheet Table 125: CID1 Register Bits Bit Name Reset RW 31:0 CID1 0xe0 R0 Description Component Identification 1. 3.7.2.
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Apollo3 Blue Datasheet Table 129: CID3 Register Bits Bit Name Reset RW 31:0 CID3 0xb1 R0 Description Component Identification 3. 3.8 MCUCTRL Registers MCU Miscellaneous Control Logic INSTANCE 0 BASE ADDRESS:0x40020000 DS-A3-0p9p1 Page 122 of 909 2019 Ambiq Micro, Inc. All rights reserved.
PAGE 123
Apollo3 Blue Datasheet 3.8.
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Apollo3 Blue Datasheet Table 130: MCUCTRL Register Map Address(s) DS-A3-0p9p1 Register Name Description 0x40020264 OTAPOINTER OTA (Over the Air) Update Pointer/Status. Reset only by POA 0x40020280 APBDMACTRL DMA Control Register.
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Apollo3 Blue Datasheet 3.8.2 MCUCTRL Registers 3.8.2.1 CHIPPN Register Chip Information Register OFFSET: 0x00000000 INSTANCE 0 ADDRESS: 0x40020000 Chip Information Register Table 131: CHIPPN Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 PARTNUM Table 132: CHIPPN Register Bits Bit Name Reset RW Description BCD part number. 31:0 3.8.2.
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Apollo3 Blue Datasheet Table 133: CHIPID0 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CHIPID0 Table 134: CHIPID0 Register Bits Bit Name Reset RW 31:0 CHIPID0 0x0 RO Description Unique chip ID 0. APOLLO3 = 0x0 - Apollo3 CHIPID0. 3.8.2.
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Apollo3 Blue Datasheet Table 137: CHIPREV Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 RSVD 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 SIPART 0 6 0 5 0 4 0 3 REVMAJ 0 2 0 1 0 0 REVMIN Table 138: CHIPREV Register Bits Bit Name Reset RW 31:20 RSVD 0x0 RO 19:8 SIPART 0x0 RO Description RESERVED. Silicon Part ID Major Revision ID. 7:4 REVMAJ 0x0 RO B = 0x2 - Apollo3 revision B A = 0x1 - Apollo3 revision A Minor Revision ID.
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Apollo3 Blue Datasheet 3.8.2.
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Apollo3 Blue Datasheet Table 144: FEATUREENABLE Register Bits Bit Name Reset RW 31:7 RSVD 0x0 RO Description RESERVED. Availability of Burst functionality 6 BURSTAVAIL 0x0 RO 5 BURSTACK 0x0 RO AVAIL = 0x1 - Burst functionality available NOTAVAIL = 0x0 - Burst functionality not available ACK for BURSTREQ Controls the Burst functionality 4 BURSTREQ 0x0 RW 3 RSVD 0x0 RO EN = 0x1 - Enable the Burst functionality DIS = 0x0 - Disable the Burst functionality RESERVED.
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Apollo3 Blue Datasheet Table 146: DEBUGGER Register Bits Bit Name Reset RW 31:1 RSVD 0x0 RO 0 LOCKOUT 0x0 RW 3.8.2.9 Description RESERVED Lockout of debugger (SWD).
PAGE 131
Apollo3 Blue Datasheet 3.8.2.
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Apollo3 Blue Datasheet Table 152: ADCCAL Register Bits Bit Name Reset RW 31:2 RSVD 0x0 RO 1 ADCCALIBRATED Description RESERVED. Status for ADC Calibration 0x0 RO FALSE = 0x0 - ADC is not calibrated TRUE = 0x1 - ADC is calibrated Run ADC Calibration on initial power up sequence 0 CALONPWRUP 0x1 RW DIS = 0x0 - Disable automatic calibration on initial power up EN = 0x1 - Enable automatic calibration on initial power up 3.8.2.
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Apollo3 Blue Datasheet Table 155: ADCTRIM Register 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 RSVD 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 2 0 1 0 0 ADCREFKEEPIBTRIM 2 9 ADCREFBUFTRIM 3 0 ADCRFBUFIBTRIM 3 1 RSVD Table 156: ADCTRIM Register Bits Bit Name Reset RW 31:13 RSVD 0x0 RO 12:11 ADCRFBUFIBTRIM 0x0 RW 10:6 ADCREFBUFTRIM 0x8 RW 5:2 RSVD 0x0 RO 1:0 ADCREFKEEPIBTRIM 0x0 RW Description RESERVED.
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Apollo3 Blue Datasheet Table 158: ADCREFCOMP Register Bits Bit Name Reset RW 31:17 RSVD 0x0 RO 16 ADCRFCMPEN 0x0 RW 15:13 RSVD 0x0 RO 12:8 ADCREFKEEPTRIM 0x0 RW 7:1 RSVD 0x0 RO 0 ADC_REFCOMP_OUT 0x0 RO Description RESERVED ADC Reference comparator power down RESERVED ADC Reference Keeper Trim RESERVED Output of the ADC reference comparator 3.8.2.
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Apollo3 Blue Datasheet Table 160: XTALCTRL Register Bits Bit Name Reset RW Description XTAL Power down on brown out. 5 PWDBODXTAL 4 PDNBCMPRXTAL 3 PDNBCOREXTAL 0x0 RW PWRUPBOD = 0x0 - Power up xtal on BOD PWRDNBOD = 0x1 - Power down XTAL on BOD. XTAL Oscillator Power Down Comparator. 0x1 RW PWRUPCOMP = 0x1 - Power up XTAL oscillator comparator. PWRDNCOMP = 0x0 - Power down XTAL oscillator comparator. XTAL Oscillator Power Down Core. 0x1 RW PWRUPCORE = 0x1 - Power up XTAL oscillator core.
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Apollo3 Blue Datasheet Table 162: XTALGENCTRL Register Bits Bit Name Reset RW 31:14 RSVD 0x0 RO 13:8 XTALKSBIASTRIM 0x1 RW 7:2 XTALBIASTRIM 0x0 RW Description RESERVED. XTAL IBIAS Kick start trim. This trim value is used during the startup process to enable a faster lock.
PAGE 137
Apollo3 Blue Datasheet 3.8.2.
PAGE 138
Apollo3 Blue Datasheet Table 166: BOOTLOADER Register Bits Bit Name Reset 0 BOOTLOADERLOW RW 0x1 RW Description Determines whether the bootloader code is visible at address 0x00000000 or not. Resets to 1, write 1 to clear. ADDR0 = 0x1 - Bootloader code at 0x00000000. 3.8.2.19 SHADOWVALID Register Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space.
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Apollo3 Blue Datasheet INSTANCE 0 ADDRESS: 0x400201B0 Scratch register that is not reset by any reset Table 169: SCRATCH0 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 SCRATCH0 Table 170: SCRATCH0 Register Bits Bit Name Reset RW 31:0 SCRATCH0 0x0 RW Description Scratch register 0. 3.8.2.
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Apollo3 Blue Datasheet Table 173: ICODEFAULTADDR Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ICODEFAULTADDR Table 174: ICODEFAULTADDR Register Bits Bit Name Reset 31:0 ICODEFAULTADDR RW 0x0 Description The ICODE bus address observed when a Bus Fault occurred.
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Apollo3 Blue Datasheet Table 177: SYSFAULTADDR Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 SYSFAULTADDR Table 178: SYSFAULTADDR Register Bits Bit Name Reset 31:0 SYSFAULTADDR RW 0x0 RO Description SYS bus address observed when a Bus Fault occurred.
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Apollo3 Blue Datasheet Table 180: FAULTSTATUS Register Bits Bit Name 1 Reset DCODEFAULT RW 0x0 RW Description DCODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the DCODEFAULTADDR register will contain the bus address which generated the fault. NOFAULT = 0x0 - No DCODE fault has been detected. FAULT = 0x1 - DCODE fault detected. 0 ICODEFAULT 0x0 RW The ICODE Bus Decoder Fault Detected bit.
PAGE 143
Apollo3 Blue Datasheet 3.8.2.
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Apollo3 Blue Datasheet Control bit to enable/disable the PMU Table 187: PMUENABLE Register 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ENABLE 3 1 RSVD Table 188: PMUENABLE Register Bits Bit Name Reset RW 31:1 RSVD 0x0 RO 0 ENABLE 0x1 RW Description RESERVED. PMU Enable Control bit.
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Apollo3 Blue Datasheet Table 190: TPIUCTRL Register Bits Bit Name Reset RW Description This field selects the frequency of the ARM M4 TPIU port. 10:8 CLKSEL 0x0 RW 7:1 RSVD 0x0 RO 0 ENABLE 0x0 RW LOWPWR = 0x0 - Low power state.
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Apollo3 Blue Datasheet Table 192: OTAPOINTER Register Bits Bit Name Reset RW 0 OTAVALID 0x0 RW Description Indicates that an OTA update is valid 3.8.2.32 APBDMACTRL Register DMA Control Register. Determines misc settings for DMA operation OFFSET: 0x00000280 INSTANCE 0 ADDRESS: 0x40020280 DMA Control Register.
PAGE 147
Apollo3 Blue Datasheet 3.8.2.
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Apollo3 Blue Datasheet Key Register to enable the use of external clock selects via the EXTCLKSEL reg Table 197: KEXTCLKSEL Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 KEXTCLKSEL Table 198: KEXTCLKSEL Register Bits Bit Name Reset RW 31:0 KEXTCLKSEL 0x0 RW Description Key register value. Key = 0x53 - Key 3.8.2.
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Apollo3 Blue Datasheet Table 200: SIMOBUCK4 Register Bits Bit Name Reset RW Description simobuck_uvlo_mode. In B0, these bits are used as SIMOBUCK mode bits. uvlo_mode[0] enables use of tonclk_lp for all operations and uvlo_mode[1] controls core_low/mem_low synchronization.
PAGE 150
Apollo3 Blue Datasheet 3.8.2.
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Apollo3 Blue Datasheet Table 204: FLASHWPROT0 Register Bits Bit Name 31:0 Reset FW0BITS RW 0x0 RW Description Write protect flash 0x00000000 - 0x0007FFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset) 3.8.2.
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Apollo3 Blue Datasheet Table 208: FLASHRPROT0 Register Bits Bit Name 31:0 Reset FR0BITS RW 0x0 RW Description Copy (read) protect flash 0x00000000 - 0x0007FFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset) 3.8.2.
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Apollo3 Blue Datasheet Table 212: DMASRAMWRITEPROTECT0 Register Bits Bit Name 31:0 Reset DMA_WPROT0 RW 0x0 RW Description Write protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA writes, when set to 0, DMA may write the region. 3.8.2.42 DMASRAMWRITEPROTECT1 Register SRAM write-protection bits.
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Apollo3 Blue Datasheet Table 216: DMASRAMREADPROTECT0 Register Bits Bit Name 31:0 Reset DMA_RPROT0 RW 0x0 RW Description Read protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA reads, when set to 0, DMA may read the region. 3.8.2.44 DMASRAMREADPROTECT1 Register SRAM read-protection bits. OFFSET: 0x000003D4 INSTANCE 0 ADDRESS: 0x400203D4 These bits read-protect system SRAM from DMA operations in 8KB chunks.
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32KB SRAM 32KB SRAM 32KB SRAM 32KB SRAM 32KB SRAM 32KB SRAM 32KB SRAM 32KB SRAM 24KB SRAM 8KB SRAM 32KB SRAM 32KB SRAM 32KB SRAM Apollo3 Blue Datasheet Instruction ARM M4 Core Data AHB Fabric Boot Loader ROM SYS Flash Cache APB Flash & OTP Control Up To 64MB External Flash Instance Bridge 512KB Flash 512KB Flash Instance Instance 16KB OTP Figure 5. Block Diagram for Flash and OTP Memory Subsystem 3.9.
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Apollo3 Blue Datasheet ▪ 2 instances of 512 KB flash Memory (up to 1 MB total) ▪ 16 KB Flash cache (2-way set-associative/Direct Mapped, 512 entry, 128b linesize) ▪ 16 KBytes OTP - 8 KBytes contain factory preset per chip trim values.
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Apollo3 Blue Datasheet 3.9.3 3.9.3.1 Flash Cache Functional Overview Figure 6. Block Diagram for Apollo3 Blue MCU with Flash Cache Apollo3 Blue MCU incorporates a Flash cache to the ICode and DCode path from the microcontroller. This controller is intended to provide single cycle read access to Flash and reduce overall accesses to the Flash to reduce power. The controller is a unified ICode and DCode cache controller.
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Apollo3 Blue Datasheet 3.9.3.1.1 Cache Operation To enable the cache, software should write the CACHECFG register with the desired setting. The ENABLE field in this register will power up the cache SRAMs and initiate the cache startup sequence which will flush the cache RAMs.
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Apollo3 Blue Datasheet 3.9.3.2.
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Apollo3 Blue Datasheet 3.9.3.2.2 CACHECTRL Registers 3.9.3.2.2.
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Apollo3 Blue Datasheet Table 221: CACHECFG Register Bits Bit Name Reset RW Description Sets the cache configuration 7:4 CONFIG 0x5 RW 3 ENABLE_NC1 0x0 RW 2 ENABLE_NC0 0x0 RW 1 LRU 0x0 RW 0 ENABLE 0x0 RW W1_128B_512E = 0x4 - Direct mapped, 128-bit linesize, 512 entries (4 SRAMs active) W2_128B_512E = 0x5 - Two-way set associative, 128-bit linesize, 512 entries (8 SRAMs active) W1_128B_1024E = 0x8 - Direct mapped, 128-bit linesize, 1024 entries (8 SRAMs active) Enable Non-cacheable r
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Apollo3 Blue Datasheet Table 223: FLASHCFG Register Bits Bit Name Reset RW Description Controls flash low power modes (control of LPM pin). 13:12 LPMMODE 0x0 RW 11:8 LPM_RD_WAIT 0x8 RW 7 RSVD 0x0 RO 6:4 SEDELAY 0x7 RW 3:0 RD_WAIT 0x3 RW NEVER = 0x0 - High power mode (LPM not used). STANDBY = 0x1 - Fast Standby mode. LPM deasserted for read operations, but asserted while flash IDLE. ALWAYS = 0x2 - Low Power mode. LPM always asserted for reads.
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Apollo3 Blue Datasheet Table 225: CTRL Register Bits Bit Name 10 FLASH1_SLM_ ENABLE 0x0 WO 9 FLASH1_SLM_DISABLE 0x0 WO Disable Flash Sleep Mode. Write 1 to wake flash1 from sleep mode (reading the array will also automatically wake it). 8 FLASH1_SLM_ STATUS 0x0 RO Flash Sleep Mode Status. 1 indicates that flash1 is in sleep mode, 0 indicates flash1 is in normal mode. 7 RSVD 0x0 RO 6 FLASH0_SLM_ ENABLE 0x0 WO 5 FLASH0_SLM_DISABLE 0x0 WO Disable Flash Sleep Mode.
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Apollo3 Blue Datasheet Table 227: NCR0START Register Bits Bit Name Reset RW 31:27 RSVD 0x0 RO 26:4 ADDR 0x0 RW 3:0 RSVD 0x0 RO Description This bitfield is reserved for future use. Start address for non-cacheable region 0 This bitfield is reserved for future use. 3.9.3.2.2.
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Apollo3 Blue Datasheet Table 230: NCR1START Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 RSVD 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 ADDR 0 2 0 1 0 0 RSVD Table 231: NCR1START Register Bits Bit Name Reset RW 31:27 RSVD 0x0 RO 26:4 ADDR 0x0 RW 3:0 RSVD 0x0 RO Description This bitfield is reserved for future use. Start address for non-cacheable region 1 This bitfield is reserved for future use. 3.9.3.2.2.
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Apollo3 Blue Datasheet INSTANCE 0 ADDRESS: 0x40018040 Data Cache Total Accesses Table 234: DMON0 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 DACCESS_COUNT Table 235: DMON0 Register Bits Bit Name Reset RW Description 31:0 DACCESS_COUNT 0x0 RO Total accesses to data cache. All performance metrics should be relative to the number of accesses performed. 3.9.3.2.2.
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Apollo3 Blue Datasheet Table 238: DMON2 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 DHIT_COUNT Table 239: DMON2 Register Bits Bit Name Reset RW 31:0 DHIT_COUNT 0x0 RO Description Cache hits from lookup operations. 3.9.3.2.2.
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Apollo3 Blue Datasheet Table 242: IMON0 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 IACCESS_COUNT Table 243: IMON0 Register Bits Bit Name Reset RW 31:0 IACCESS_COUNT 0x0 RO Description Total accesses to Instruction cache 3.9.3.2.2.
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Apollo3 Blue Datasheet Table 246: IMON2 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 IHIT_COUNT Table 247: IMON2 Register Bits Bit Name Reset RW 31:0 IHIT_COUNT 0x0 RO Description Cache hits from lookup operations 3.9.3.2.2.
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Apollo3 Blue Datasheet 3.9.3.3 Flash Memory Controller Figure 7. Block diagram for the Flash Memory Controller AHB Slave (ICode) AHB Slave (DCode) AHB Slave (Info Space) Request Translator Request Translator Request Translator Flash Instance APB Slave (Control Regs) Control Registers Timing Control APB Slave (Config Regs) Config Registers Copy Engine Request Translator 3.9.3.3.
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Apollo3 Blue Datasheet same line should not be exceeded. Doing more than the restricted number of program cycles to the same line between erase operations may cause data corruption/retention issues within the word line. 3.9.4 SRAM Interface 3.9.4.1 Functional Overview Figure 8.
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Apollo3 Blue Datasheet states and can operate up to the maximum operating frequency of the CPU core. On Apollo3, the DTCM banks are guaranteed to be zero wait-state unless there is contention for that specific memory array with another requestor (CPU I/D Bus or DMA Bus). The Main SRAM banks are zero wait-state for sequential accesses or 1-wait state for non-sequential accesses for I/D Bus accesses unless there is contention for that specific memory array with another requestor (CPU I/D Bus or DMA Bus).
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Apollo3 Blue Datasheet 4. Security 4.1 Functional Overview The Apollo3 Blue MCU includes the following security features: ▪ ▪ ▪ ▪ ▪ ▪ ▪ Secure Boot Secure OTA Secure Key Storage Key Revocation AES128, SHA256 CRC32 External Flash Inline Encryption/Decryption More details on the Apollo3 Blue MCU security features are described in the Ambiq Apollo3 Blue MCU Security Whitepaper. 4.2 Secure Boot The Secure Boot feature on the Apollo3 Blue MCU provides a secure foundation for customer firmware.
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Apollo3 Blue Datasheet 4.3 Secure OTA Apollo3 Blue MCU supports secure OTA leveraging the Ambiq secure boot loader. Customers can update any firmware component securely as directed via the security policy configuration in OTP. The basic flow is shown in Figure 10. Initiate OTA Download Secure Blob(s) Register OTA Downloads with Secure OTA Installer yes Secure OTA Verification/ Decryption/Installation Error ERROR Additional OTA Updates? no Initiate Secure Boot with New Image Figure 10.
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Apollo3 Blue Datasheet The Ambiq secure inline encrypt/decrypt provides robust, high performance and extremely low power protection for external flash contents. Ambiq’s inline encrypt/decrypt enables truly inline capability that does not degrade performance when asking external flash. For more details on the inline support, See “MSPI Master Module” on page 216. DS-A3-0p9p1 Page 175 of 909 2019 Ambiq Micro, Inc. All rights reserved.
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Apollo3 Blue Datasheet 5. DMA 5.1 Functional Overview The Apollo3 Blue MCU supports DMA capability for the following peripheral controllers: ▪ ▪ ▪ ▪ ▪ ▪ ▪ SPI Master I2C Master PDM ADC MSPI BLE Security DMA is supported from peripheral to SRAM and SRAM/Flash to peripheral. DMA transactions to/from SRAM occur concurrently to CPU instruction/data accesses as long as the accesses are to different physical banks of memory. Accesses to the same physical bank are arbitrated in hardware.
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Apollo3 Blue Datasheet 5.1.2 Auto Power Down The DMA-capable peripherals can be configured to automatically power down the respective peripheral device once the total DMA transaction is complete. This feature is particularly useful in cases where a device transaction can be queued up allowing the CPU to go into deep sleep while the transaction completes which could take a long time depending on the data rate of the device and/or the trigger conditions for sending/receiving data.
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Apollo3 Blue Datasheet 6. BLE Module RC 32MHz XTAL 32MHz Cmd Queue Pwr Mgt DMA 128kB ROM BLE 32b Controller Bus Interface 42kB RAM Regs RF Modem Baseband Security INTs Figure 11. Block Diagram for the BLE Module 6.1 Functional Overview 6.1.1 Introduction The Apollo3 Blue MCU includes a low power Bluetooth low energy subsystem. The BLE controller and host can be configured to support up to eight simultaneous connections. Secure connections and extended packet length are also supported.
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Apollo3 Blue Datasheet ▪ External Power Amplifier support ▪ Integrated Balun and antenna matching network 6.2 Functional Description The BLE subsystem is a fully integrated system providing autonomous clock and power management. The subsystem is accessed via the BLE interface block. Software leverages the fully HCI compliant interface for Bluetooth operation. A series of proprietary HCI commands are also leveraged to provide additional performance and low power operation.
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Apollo3 Blue Datasheet register meets the data criteria. Because the MCU access to the interface is 32b wide, only the word count of the selected THR is used, and the low order bits of the FIFOWTHR or FIFORTHR are ignored. During the transfer, the TOTCOUNT register is decremented to reflect the number of bytes transferred. For BLE write operations (data written from BLEIF into the BLE Core), the THR trigger will activate when the write FIFO contains FIFOWTHR[5:2] free words.
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Apollo3 Blue Datasheet 6.3.
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Apollo3 Blue Datasheet Table 250: BLEIF Register Map Address(es) DS-A3-0p9p1 Register Name Description 0x5000C308 PWRCMD BLE Power command interface 0x5000C30C BSTATUS BLE Core status 0x5000C410 BLEDBG BLEIF Master Debug Register Page 182 of 909 2019 Ambiq Micro, Inc. All rights reserved.
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Apollo3 Blue Datasheet 6.3.2 BLEIF Registers 6.3.2.1 FIFO Register FIFO Access Port OFFSET: 0x00000000 INSTANCE 0 ADDRESS: 0x5000C000 Provides direct random access to both input and output fifos. The state of the FIFO is not disturbed by reading these locations (i.e., no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C, and is used for data output from the IOM to external devices. These FIFO locations can be read and written directly.
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Apollo3 Blue Datasheet Table 254: FIFOPTR Register Bits Bit Name Reset RW Description 31:24 FIFO1REM 0x0 RO The number of remaining data bytes slots currently in FIFO 1 (written by interface, read by MCU) 23:16 FIFO1SIZ 0x0 RO The number of valid data bytes currently in FIFO 1 (written by interface, read by MCU) 15:8 FIFO0REM 0x0 RO The number of remaining data bytes slots currently in FIFO 0 (written by MCU, read by interface) 7:0 FIFO0SIZ 0x0 RO The number of valid data bytes curr
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Apollo3 Blue Datasheet Table 256: FIFOTHR Register Bits Bit Name 5:0 Reset FIFORTHR 6.3.2.4 RW 0x0 RW Description FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data, as indicated by the FIFO1SIZ field.
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Apollo3 Blue Datasheet Table 260: FIFOPUSH Register Bits Bit Name 31:0 Reset FIFODIN 6.3.2.6 RW 0x0 RW Description This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes). FIFOCTRL Register FIFO Control Register OFFSET: 0x00000110 INSTANCE 0 ADDRESS: 0x5000C110 Provides controls for the operation of the internal FIFOs.
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Apollo3 Blue Datasheet Table 263: FIFOLOC Register 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 RSVD 0 6 0 5 0 4 0 3 0 2 0 1 0 0 FIFOWPTR 3 0 FIFORPTR 3 1 RSVD Table 264: FIFOLOC Register Bits Bit Name Reset RW 31:12 RSVD 0x0 RO 11:8 FIFORPTR 0x0 RW 7:4 RSVD 0x0 RO 3:0 FIFOWPTR 0x0 RW 6.3.2.8 Description Reserved Current FIFO read pointer.
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Apollo3 Blue Datasheet Table 266: CLKCFG Register Bits Bit Name Reset RW 31:13 RSVD 0x0 RO 12 DIV3 0x0 RW 11 CLK32KEN 0x0 RW Description RESERVED Enable of the divide by 3 of the source IOCLK. Enable for the 32Khz clock to the BLE module Select the input clock frequency. 10:8 FSEL 0x0 RW 7:1 RSVD 0x0 RO 0 IOCLKEN 0x0 RW 6.3.2.9 MIN_PWR = 0x0 - Selects the minimum power clock. This setting should be used whenever the IOM is not active.
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Apollo3 Blue Datasheet Table 268: CMD Register Bits Bit Name Reset RW Description This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command. Offset bytes are transferred starting from the highest byte first. 31:24 OFFSETLO 0x0 RW 23:22 RSRVD54 0x0 RO 21:20 CMDSEL 0x0 RW 19:8 TSIZE 0x0 RW Defines the transaction size in bytes. The offset transfer is not included in this size.
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Apollo3 Blue Datasheet Table 270: CMDRPT Register Bits Bit Name Reset RW 31:5 RSVD 0x0 RO 4:0 CMDRPT 0x0 RW Description RESERVED Count of number of times to repeat the next command. 6.3.2.11 OFFSETHI Register High order offset bytes OFFSET: 0x00000214 INSTANCE 0 ADDRESS: 0x5000C214 Provides the high order bytes of 2 or 3 byte offset transactions of the current command. Usage of these bytes is dependent on the offsetcnt field in the CMD register.
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Apollo3 Blue Datasheet Table 273: CMDSTAT Register 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 RSRVD0 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 CMDSTAT 3 1 CTSIZE 0 2 0 1 0 0 CCMD Table 274: CMDSTAT Register Bits Bit Name Reset RW 31:20 RSRVD0 0x0 RO 19:8 CTSIZE 0x0 RO Description Reserved The current number of bytes still to be transferred with this command. This field will count down to zero.
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Apollo3 Blue Datasheet Table 276: INTEN Register Bits Bit Name Reset RW 31:17 RSVD 0x0 RO 16 B2MSHUTDN 0x0 RW 15 B2MACTIVE 0x0 RW 14 B2MSLEEP 0x0 RW 13 12 11 CQERR CQUPD CQPAUSED 0x0 0x0 0x0 RW RW RW 10 DERR 0x0 RW 9 DCMP 0x0 RW Description RESERVED Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state. Revision B: Falling BLE Core Status signal.
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Apollo3 Blue Datasheet Table 276: INTEN Register Bits Bit Name Reset RW Description 4 B2MST 0x0 RW B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core. 3 FOVFL 0x0 RW Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop. 2 FUNDFL 0x0 RW Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO. 1 THR 0x0 RW FIFO Threshold interrupt.
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Apollo3 Blue Datasheet Table 278: INTSTAT Register Bits Bit Name Reset RW 15 B2MACTIVE 0x0 RW 14 B2MSLEEP 0x0 RW 13 12 11 CQERR CQUPD CQPAUSED 0x0 0x0 0x0 RW RW RW 10 DERR 0x0 RW 9 DCMP 0x0 RW Description Revision A: The B2M_STATE from the BLE Core transitioned into the active state. Revision B: Falling BLE Core IRQ signal.
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Apollo3 Blue Datasheet Table 278: INTSTAT Register Bits Bit Name Reset RW Description 1 THR 0x0 RW FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. 0 CMDCMP 0x0 RW Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed. 6.3.2.
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Apollo3 Blue Datasheet Table 280: INTCLR Register Bits Bit 12 11 Name Reset CQUPD CQPAUSED 0x0 0x0 RW RW RW 10 DERR 0x0 RW 9 DCMP 0x0 RW Description Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.
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Apollo3 Blue Datasheet INSTANCE 0 ADDRESS: 0x5000C22C Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
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Apollo3 Blue Datasheet Table 282: INTSET Register Bits Bit Name Reset RW Description 9 DCMP 0x0 RW DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. 8 BLECSSTAT 0x0 RW 7 BLECIRQ 0x0 RW BLE Core IRQ signal.
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Apollo3 Blue Datasheet 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 RSVD 0 1 0 0 DTHREN 3 1 DCMDCMPEN Table 283: DMATRIGEN Register Table 284: DMATRIGEN Register Bits Bit Name Reset RW 31:2 RSVD 0x0 RO 1 DTHREN 0 0x0 DCMDCMPEN RW 0x0 RW Description RESERVED. Trigger DMA upon THR level reached.
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Apollo3 Blue Datasheet Table 286: DMATRIGSTAT Register Bits Bit Name Reset RW 31:3 RSVD 0x0 RO Description RESERVED. DMA triggered when DCMDCMP = 0, and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is 2 DTOTCMP 0x0 RO 1 DTHR 0x0 RO Triggered DMA from THR event.
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Apollo3 Blue Datasheet Table 288: DMACFG Register Bits Bit Name Reset RW 7:2 RSVD 0x0 RO Description RESERVED. Direction 1 DMADIR 0x0 RW P2M = 0x0 - Peripheral to Memory (SRAM) transaction. To be set when doing IOM read operations, i.e., reading data from external devices. M2P = 0x1 - Memory to Peripheral transaction. To be set when doing IOM write operations, i.e., writing data to external devices. DMA Enable. Setting this bit to EN will start the DMA operation.
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Apollo3 Blue Datasheet The source or destination address internal the SRAM for the DMA data.
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Apollo3 Blue Datasheet Table 294: DMASTAT Register Bits Bit Name Reset RW 31:3 RSVD 0x0 RO 2 DMAERR 0x0 RW DMA Error. This active high bit signals that an error was encountered during the DMA operation. 1 DMACPL 0x0 RW DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0. 0 DMATIP 0x0 RO Description RESERVED. DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active.
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Apollo3 Blue Datasheet 6.3.2.24 CQADDR Register CQ Target Read Address Register OFFSET: 0x0000024C INSTANCE 0 ADDRESS: 0x5000C24C The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses, and is the live version of the register.
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Apollo3 Blue Datasheet 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 RSVD 0 2 0 1 0 0 CQTIP 3 0 CQPAUSED 3 1 CQERR Table 299: CQSTAT Register Table 300: CQSTAT Register Bits Bit Name Reset RW 31:3 RSVD 0x0 RO 2 CQERR 0x0 RW 1 CQPAUSED 0x0 RO 0 CQTIP 0x0 RO Description RESERVED. Command queue processing error.
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Apollo3 Blue Datasheet Table 302: CQFLAGS Register Bits Bit Name Reset RW 31:16 CQIRQMASK 0x0 RW 15:0 CQFLAGS 0x0 RO Description Provides for a per-bit mask of the flags used to invoke an interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt, if the CQWT_int interrupt is enabled. Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status. 6.3.2.
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Apollo3 Blue Datasheet Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1', CQ processing will halt until either value is changed to '0'.
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Apollo3 Blue Datasheet INSTANCE 0 ADDRESS: 0x5000C260 Current index value, targeted to be written by register write operations within the command queue.
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Apollo3 Blue Datasheet Table 310: CQENDIDX Register Bits Bit Name 7:0 Reset CQENDIDX RW 0x0 RW Description Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN. 6.3.2.31 STATUS Register IOM Module Status Register OFFSET: 0x00000268 INSTANCE 0 ADDRESS: 0x5000C268 General status of the IOM module command execution.
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Apollo3 Blue Datasheet INSTANCE 0 ADDRESS: 0x5000C300 Controls the configuration of the SPI master module, including POL/PHA, LSB, flow control, and delays for MISO and MOSI 2 1 2 0 1 9 RSVD 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 RSVD 0 6 0 5 0 4 0 3 0 2 0 1 0 0 SPOL 2 2 SPHA 2 3 FULLDUP 2 4 WTFC 2 5 RDFC 2 6 WTF- 2 7 SPILSB 2 8 RDFCPOL RSVD 2 9 DINDLY 3 0 DOUTDLY 3 1 MSPIRST Table 313: MSPICFG Register Table 314: MSPICFG Register Bits Bit Name Rese
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Apollo3 Blue Datasheet Table 314: MSPICFG Register Bits Bit Name Reset RW Description Enables flow control of new read transactions based on the SPI_STATUS signal from the BLE Core. 17 RDFC 0x0 RW DIS = 0x0 - Read mode flow control disabled. EN = 0x1 - Read mode flow control enabled. Enables flow control of new write transactions based on the SPI_STATUS signal from the BLE Core. 16 WTFC 0x0 RW DIS = 0x0 - Write mode flow control disabled. EN = 0x1 - Write mode flow control enabled.
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Apollo3 Blue Datasheet Table 316: BLECFG Register Bits Bit Name Reset RW Description Configuration of BLEH isolation controls for SPI related signals. 15:14 SPIISOCTL 0x0 RW ON = 0x3 - SPI signals from BLE Core to/from MCU Core are isolated. OFF = 0x2 - SPI signals from BLE Core to/from MCU Core are not isolated. AUTO = 0x0 - SPI signals from BLE Core to/from MCU Core are automatically isolated by the logic Configuration of BLEH isolation control for power related signals.
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Apollo3 Blue Datasheet Table 316: BLECFG Register Bits Bit Name Reset RW Description Enable the power state machine for automatic sequencing and control of power states of the BLE Core module. 0 PWRSMEN 0x0 RW ON = 0x1 - Internal power state machine is enabled and will sequence the BLEH power domain as indicated in the design document. Overrides for the power signals are not enabled. OFF = 0x0 - Internal power state machine is disabled and will not sequence the BLEH power domain.
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Apollo3 Blue Datasheet 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 RSVD 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 PWRST 0 5 0 4 0 3 0 2 0 1 0 0 B2MSTATE 2 5 SPISTATUS 2 6 DCDCREQ 2 7 WAKEUP 2 8 DCDCFLAG 2 9 BLEIRQ 3 0 BLEHACK 3 1 BLEHREQ Table 319: BSTATUS Register Table 320: BSTATUS Register Bits Bit Name Reset RW 31:13 RSVD 0x0 RO 12 BLEHREQ 0x0 RO 11 BLEHACK 0x0 RO Description RESERVED Value of the BLEHREQ signal to the power control unit.
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Apollo3 Blue Datasheet Table 320: BSTATUS Register Bits Bit Name Reset RW Description State of the BLE Core logic. 2:0 B2MSTATE 0x0 RO RESET = 0x0 - Reset State Shutdown = 0x0 - Shutdown state Sleep = 0x1 - Sleep state. Standby = 0x2 - Standby State Idle = 0x3 - Idle state Active = 0x4 - Active state. 6.3.2.
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Apollo3 Blue Datasheet 7. MSPI Master Module DMA XiP CMD Queue 1 / 2 / 4 / 8 bit I/O MSPI Controller REGs Bus Interface Rx FIFO Tx FIFO INTs Figure 12. Block Diagram for the MSPI Master Module 7.1 Functional Overview The Apollo3 MCU includes a Multi-bit SPI (MSPI) module which can be used to connect to external serial memory devices.
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Apollo3 Blue Datasheet 7.2 Configuration The MSPI module should be configured to match the transfer characteristics of the external device(s) on the bus. Generally, the configuration sequence would proceed as follows: ▪ Configure MSPI clock divider (MSPICFG register). The MSPI's reference frequency is 48MHz, so the resulting clock frequency is 48/CLKDIV value.
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Apollo3 Blue Datasheet 7.3.1 Paired-Quad Device Operation (QUADCMD) Using a single serial, dual, quad, or octal device is fairly straightforward since all data and commands sent to the device are transmitted and received as a string of serialized bytes.
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Apollo3 Blue Datasheet 7.4 DMA Operations The MSPI controller tightly integrates the DMA controller with the transfer interface and automatically handles sequencing of instructions and address to serial flash device and the subsequent transfer of data to/from system memory. Before starting DMA operations, software should have already configured the CFG register (to specify device configuration) and the FLASH register (to specify the template used for DMA operations).
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Apollo3 Blue Datasheet 7.5 Execute in Place (XIP) Operations The XIP mode of operation allows devices on the MSPI interface to be mapped into the flash cache's address space and appear as an extension to the internal flash array(s). Once enabled by the XIPEN bit in the FLASH register, the flash/cache module will decode the address region and forward operations to the MSPI interface for completion.
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Apollo3 Blue Datasheet 7.5.3 Micron XIP Support Micron flash devices support an XIP mode that does not require the instruction byte to be transmitted, which minimizes the access time to the device. In order to transition in and out of this mode, the MSPI controller must issue an acknowledgment of XIP mode during the first turnaround cycle for each XIP access. When transitioning into and out of XIP mode, software must set the XIPACK field of the MSPI's FLASH register appropriately.
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Apollo3 Blue Datasheet Table 323: Command Queue Example Address Data Description 0x10000 0x50014258 DMATARGADDR register address 0x10004 0x00002800 Data to write to DMATARGADDR (i.e.
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Apollo3 Blue Datasheet This can be useful when software would like intermediate interrupts as operations complete such as after each CQ index is updated. 7.6.3 Pausing CQ Operations While the basic operation of the CQ functionality is pretty straightforward, constructing more complex scenarios such as queuing of multiple operations requires additional logic to accommodate handshaking with the software managing the queue and other modules within the chip.
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Apollo3 Blue Datasheet Table 324: CQFLAGS Bit Type Mnemonic Description/Use 5 Soft SWFLAG5 Software flag 4 Soft SWFLAG4 Software flag 3 Soft SWFLAG3 Software flag 2 Soft SWFLAG2 Software flag 1 0 Soft Soft IOM1START Flag wired to IOM devices as a hard flag for intercommunication. Typically indicates that buffer 1 has been filled by MSPI and can be emptied by the IOM. IOM0START Flag wired to IOM devices as a hard flag for intercommunication.
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Apollo3 Blue Datasheet 7.6.5 MSPI and IOM Intercommunication The MSPI module and IOM modules can be linked through the command queue flags to allow a simple form of handshaking to facilitate data flow between the two modules. The MSPI only has a single pair of hardware flags dedicated to IOM communication so software must write the IOMSEL field in the MSPICFG register to select which IOM is paired with the MSPI.
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Apollo3 Blue Datasheet The MSPI supports the following external connections. The columns to the right indicate which bits are used in each configuration (S=serial, D=dual, Q=quad, QP=quad-pair, O=octal with CE#). Within the table, O=output pin, I=input pin, and X=bidirectional.
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Apollo3 Blue Datasheet Table 326: PADCFG Description Bitfield Description IN3,IN2,IN1,IN0 Allows muxing of individual bit inputs from the upper quad (MSPI data bits 7:4) into the lower quad. Typically the OUT7-4 bits would be set to match. OUT7,OUT6,OUT5,OUT4 Allows muxing of individual bit outputs from the lower quad to the upper quad. Typically the IN3-0 bits would be set to match. OUT3 Allows MSPI pin [3] to be used as the clock output.
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Apollo3 Blue Datasheet Note that bit transmission from the MSPI to the target is fairly straightforward since both the SCLK and MOSI are delayed by similar amounts (two red arrows on the left). Depending on which pins are used, there may be some skew between the SCLK and MOSI, however, it should be relatively small compared to the half-cycle of setup time.
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Apollo3 Blue Datasheet 7.10.
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Apollo3 Blue Datasheet 7.10.2 MSPI Registers 7.10.2.1 CTRL Register MSPI PIO Transfer Control/Status Register OFFSET: 0x00000000 INSTANCE 0 ADDRESS: 0x50014000 This register is used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer, and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are enabled.
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Apollo3 Blue Datasheet Table 329: CTRL Register Bits Bit Name Reset RW Description Flag indicating that the operation is a command that should be replicated to both devices in paired QUAD mode. This is typically only used when reading/writing configuration registers in paired flash devices (do not set for memory transfers). 3 QUADCMD 0x0 RW 2 BUSY 0x0 RO 1 STATUS 0x0 RO Command status: 1 indicates command has completed. Cleared by writing 1 to this bit or starting a new transfer.
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Apollo3 Blue Datasheet Table 331: CFG Register Bits Bit Name Reset RW 13:8 TURNAROUND 0x0 RW 7 SEPIO 0x0 RW 6 ISIZE 0x0 RW 5:4 ASIZE 0x0 RW Description Number of turnaound cycles (for TX->RX transitions). ENTURN or XIPENTURN bit field. Qualified by Separate IO configuration. This bit should be set when the target device has separate MOSI and MISO pins. Respective IN/OUT bits below should be set to map pins. Instruction Size Address Size.
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Apollo3 Blue Datasheet 7.10.2.
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Apollo3 Blue Datasheet 7.10.2.6 RXFIFO Register RX Data FIFO OFFSET: 0x00000014 INSTANCE 0 ADDRESS: 0x50014014 RX Data FIFO Table 338: RXFIFO Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RXFIFO Table 339: RXFIFO Register Bits Bit Name Reset RW Description 31:0 RXFIFO 0x0 RO Receive data. Data is aligned to the LSB (padded zeros on upper bits) unless BIGENDIAN is set. 7.10.
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Apollo3 Blue Datasheet 7.10.2.
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Apollo3 Blue Datasheet Table 345: THRESHOLD Register Bits Bit Name Reset RW 7:5 RSVD 0x0 RO 4:0 TXTHRESH 0x0 RW Description RESERVED Number of entries in TX FIFO that cause TXF interrupt 7.10.2.10MSPICFG Register MSPI Module Configuration OFFSET: 0x00000100 INSTANCE 0 ADDRESS: 0x50014100 Timing configuration bits for the MSPI module. PRSTN, IPRSTN, and FIFORESET can be used to reset portions of the MSPI interface in order to clear error conditions.
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Apollo3 Blue Datasheet Table 347: MSPICFG Register Bits Bit Name Reset RW Description Clock Divider. Allows dividing 48 MHz base clock by integer multiples. Enumerations are provided for common frequency, but any integer divide from 48 MHz is allowed. Odd divide ratios will result in a 33/66 percent duty cycle with a long low clock pulse (to allow longer round-trip for read data).
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Apollo3 Blue Datasheet Configuration bits for the MSPI pads. Allows pads associated with the upper quad to be mapped to corresponding bits on the lower quad. Use of Quad0 pins is recommended for optimal timing.
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Apollo3 Blue Datasheet Table 350: PADOUTEN Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 RSVD 0 4 0 3 0 2 0 1 0 0 OUTEN Table 351: PADOUTEN Register Bits Bit Name Reset RW 31:9 RSVD 0x0 RO Description RESERVED Output pad enable configuration. Indicates which pads should be driven. Bits [3:0] are Quad0 data, [7:4] are Quad1 data, and [8] is clock.
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Apollo3 Blue Datasheet Table 353: FLASH Register Bits Bit Name Reset RW Description 15:11 RSVD 0x0 RO 10:8 XIPMIXED 0x0 RW 7 XIPSENDI 0x0 RW Indicates whether XIP/AUTO DMA operations should send an instruction (see READINSTR field and ISIZE field in CFG) 6 XIPSENDA 0x0 RW Indicates whether XIP/AUTO DMA operations should send an an address phase (see DMADEVADDR register and ASIZE field in CFG) 5 XIPENTURN 0x0 RW Indicates whether XIP/AUTO DMA operations should enable TX->RX turnar
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Apollo3 Blue Datasheet Table 354: SCRAMBLING Register 3 0 2 9 SCRENABLE 3 1 2 8 2 7 2 6 2 5 2 4 2 3 2 2 RSVD 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 SCREND 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 RSVD 0 5 0 4 0 3 0 2 0 1 0 0 SCRSTART Table 355: SCRAMBLING Register Bits Bit Name Reset RW 31 SCRENABLE 0x0 RW 30:26 RSVD 0x0 RO 25:16 SCREND 0x0 RW 15:10 RSVD 0x0 RO 9:0 SCRSTART 0x0 RW Description Enables Data Scrambling Region.
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Apollo3 Blue Datasheet Table 357: INTEN Register Bits Bit Name Reset RW 31:13 RSVD 0x0 RO 12 SCRERR 0x0 RW 11 CQERR 0x0 RW 10 CQPAUSED 0x0 RW 9 CQUPD 0x0 RW 8 CQCMP 0x0 RW 7 DERR 0x0 RW 6 DCMP 0x0 RW 5 RXF 0x0 RW 4 RXO 0x0 RW 3 RXU 0x0 RW 2 TXO 0x0 RW 1 TXE 0x0 RW 0 CMDCMP 0x0 RW Description RESERVED Scrambling Alignment Error. word (4-byte) start address.
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Apollo3 Blue Datasheet 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 RSVD 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 TXE 2 0 CMDCMP 2 1 TXO 2 2 RXU 2 3 RXO 2 4 RXF 2 5 DCMP 2 6 DERR 2 7 CQCMP 2 8 CQUPD 2 9 CQERR 3 0 SCRERR 3 1 CQPAUSED Table 358: INTSTAT Register Table 359: INTSTAT Register Bits Bit Name Reset RW 31:13 RSVD 0x0 RO 12 SCRERR 0x0 RW 11 CQERR 0x0 RW 10 CQPAUSED 0x0 RW 9 CQUPD 0x0 RW 8 CQCMP 0x0 RW 7 DERR 0x0 RW 6 DCMP 0x0
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Apollo3 Blue Datasheet 7.10.2.17INTCLR Register MSPI Master Interrupts: Clear OFFSET: 0x00000208 INSTANCE 0 ADDRESS: 0x50014208 Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
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Apollo3 Blue Datasheet Table 361: INTCLR Register Bits Bit Name Reset RW 1 TXE 0x0 RW 0 CMDCMP 0x0 RW Description Transmit FIFO empty. Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signalled simultaneously 7.10.2.18INTSET Register MSPI Master Interrupts: Set OFFSET: 0x0000020C INSTANCE 0 ADDRESS: 0x5001420C Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
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Apollo3 Blue Datasheet Table 363: INTSET Register Bits Bit Name Reset RW 5 RXF 0x0 RW 4 RXO 0x0 RW 3 RXU 0x0 RW 2 TXO 0x0 RW 1 TXE 0x0 RW 0 CMDCMP 0x0 RW Description Receive FIFO full Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall) Receive FIFO underflow (only occurs when SW reads from an empty FIFO) Transmit FIFO Overflow (only occurs when SW writes to a full FIFO). Transmit FIFO empty. Transfer complete.
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Apollo3 Blue Datasheet Table 365: DMACFG Register Bits Bit Name Reset RW Description Sets the Priority of the DMA request 4:3 DMAPRI 0x0 RW LOW = 0x0 - Low Priority (service as best effort) HIGH = 0x1 - High Priority (service immediately) AUTO = 0x2 - Auto Priority (priority raised once TX FIFO empties or RX FIFO fills) Direction 2 DMADIR 0x0 RW P2M = 0x0 - Peripheral to Memory (SRAM) transaction M2P = 0x1 - Memory to Peripheral transaction DMA Enable.
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Apollo3 Blue Datasheet Table 367: DMASTAT Register Bits Bit Name 0 Reset DMATIP RW 0x0 RO Description DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data, transferring data, or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is fully complete and no further transactions will be done. 7.10.2.
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Apollo3 Blue Datasheet Table 371: DMADEVADDR Register Bits Bit Name Reset RW 31:0 DEVADDR 0x0 RW Description SPI Device address for automated DMA transactions (both read and write). 7.10.2.
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Apollo3 Blue Datasheet Table 375: DMABCOUNT Register Bits Bit Name Reset RW 31:8 RSVD 0x0 RO 7:0 BCOUNT 0x0 RW Description Reserved Burst transfer size in bytes. This is the number of bytes transferred when a FIFO trigger event occurs. Recommended values are 16 or 32. 7.10.2.25DMATHRESH Register DMA Transmit Trigger Threshhold OFFSET: 0x00000278 INSTANCE 0 ADDRESS: 0x50014278 Indicates FIFO level at which a DMA should be triggered.
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Apollo3 Blue Datasheet 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 RSVD 0 3 0 2 0 1 0 0 CQEN 2 9 CQPRI 3 0 CQPWROFF 3 1 CQAUTOCLEARMASK Table 378: CQCFG Register Table 379: CQCFG Register Bits Bit Name Reset RW 31:4 RSVD 0x0 RO 3 CQAUTOCLEARMASK 0x0 RW 2 CQPWROFF 0x0 RW Description RESERVED. Eanble clear of CQMASK after each pause operation. This may be useful when using software flags to pause CQ.
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Apollo3 Blue Datasheet Table 380: CQADDR Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 RSVD 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CQADDR Table 381: CQADDR Register Bits Bit Name Reset RW 31:29 RSVD 0x0 RO 28:0 CQADDR 0x0 RW Description Reserved Address of command queue buffer in SRAM or flash. The buffer address must be aligned to a word boundary. 7.10.2.
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Apollo3 Blue Datasheet Table 383: CQSTAT Register Bits Bit Name 0 Reset CQTIP RW 0x0 RO Description Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event. 7.10.2.
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Apollo3 Blue Datasheet Table 385: CQFLAGS Register Bits Bit Name Reset RW Description Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status. 15:0 CQFLAGS 0x0 RO STOP = 0x8000 - CQ Stop Flag. When set, CQ processing will complete. CQIDX = 0x4000 - CQ Index Pointers (CURIDX/ENDIDX) match.
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Apollo3 Blue Datasheet Table 387: CQSETCLEAR Register Bits Bit Name Reset RW 31:24 RSVD 0x0 RO 23:16 CQFCLR 0x0 WO 15:8 CQFTOGGLE 0x0 RO 7:0 CQFSET 0x0 WO Description Reserved Clear CQFlag status bits. Toggle CQFlag status bits Set CQFlag status bits. Set has priority over clear if both are high. 7.10.2.
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Apollo3 Blue Datasheet Table 389: CQPAUSE Register Bits Bit Name Reset RW Description CQ will pause processing until all specified events are satisfied. 15:0 CQMASK 0x0 RW STOP = 0x8000 - CQ Stop Flag. When set, CQ processing will complete. CQIDX = 0x4000 - CQ Index Pointers (CURIDX/ENDIDX) match.
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Apollo3 Blue Datasheet Table 391: CQCURIDX Register Bits Bit Name Reset RW 31:8 RSVD 0x0 RO 7:0 CQCURIDX 0x0 RW Description RESERVED. Can be used to indicate the current position of the command queue by having CQ operations write this field. A CQ hardware status flag indicates when CURIDX and ENDIDX are not equal, allowing SW to pause the CQ processing until the end index is updated. 7.10.2.
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Apollo3 Blue Datasheet 8. I2C/SPI Master Module SPI Master Controller DMA CMD Queue IO Mux I2C Master Controller REGs Bus Interface FIFO INTs Figure 14. Block Diagram for the I2C/SPI Master Module 8.1 Functional Overview The Apollo3 Blue MCU includes six I2C/SPI High Speed Master Modules, shown in Figure 14, each of which functions as the Master of an I2C or SPI interface as selected by the REG_IOMSTRn_IOMCFG_IFCSEL bit (n=0 or 1).
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Apollo3 Blue Datasheet 8.1.1 Main Features No resources are shared between IOM modules, but within a single IOM module, the submodules share a common set of FIFO and command resources. 8.1.1.1 - 2 Independent 32-byte FIFOs, one dedicated each direction of data transfer Direct access of all FIFO data from MCU interface, including non-destructive reads. FIFO mode read/write access (push/pop mechanism) Direct command, direct data mode.
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Apollo3 Blue Datasheet IO_CLK is used as the source of the interface clock and has selectable frequencies. The overview of the clocking structure is shown below: CLKGEN RIPPLE DIVIDERS IO_CLK HFRC FSEL CLKEN IOM MODULE IOM REGS IOM CLKGEN DMA Fabric APB IFACE DMA IOM IFC_CLK I2C FIFO SPI PIN MUX Figure 15. Clocking Structure for IOM Module The APB_CLK is an internal clock sourced from the bus fabric and operates at a fixed 24MHz frequency.
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Apollo3 Blue Datasheet Figure 16. IO_CLK Generation The divided by 3 divider is optional and will provide a 50% duty cycle divided by 3 clock. This divider is bypassed when the DIV3 field is set to 0. The output of the DIV3 module is then fed to the programmable divider. This divider can be bypassed or enabled via the DIVEN field in the CLKCFG.
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Apollo3 Blue Datasheet 8.2.3 FIFO The IOM module contains 2 uni-directional FIFOs, each 32 bytes wide. These FIFOs are used only for data storage during IO transactions. The FIFO supports both single (half duplex) and duplex modes of operation. During direct mode data transfer operations, IO data transfer between the IOM module and the MCU is done by accessing the REG_IOM_FIFOPOP and REG_IOM_FIFOPUSH registers.
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Apollo3 Blue Datasheet WRITE FIFO AFTER DIRECT MODE PUSH OF 2 WORDS (0x87654321, 0x0FEDCBA9) WRITE FIFO INIT STATE FIFO PTR FIFO LOCATION 0 FIFO LOCATION 1 FIFO LOCATION 2 21 43 word 0 65 FIFO LOCATION 3 FIFO LOCATION 6 65 CB ED FIFO PTR DISCARDED BYTES word 1 word 2 FIFO LOCATION 10 FIFO LOCATION 10 9A CB ED FIFO PTR FIFO LOCATION 8 FIFO LOCATION 9 word 2 FIFO LOCATION 10 FIFO LOCATION 10 …………………….. …………………….. ……………………..
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Apollo3 Blue Datasheet 8.2.4.2 DMA Data transfers DMA transfers are enabled by configuring the DMA related registers, enabling the DMA channel, and then issuing the command. The command will automatically fetch and store the data associated with the command without MCU intervention. The DMA channel is enabled via the REG_IOM_DMACFG.DMAEN field. P2M DMA operations transfer data from peripheral to memory and are used in IOM READ operations.
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Apollo3 Blue Datasheet - REG_IOM_DMATARGADDR – The source or destination address of the DMA data. Sources can be either SRAM or FLASH. Destination address can only be SRAM. This is the memory mapped address of the DMA data as accessed by the MCU. After the module setup is complete, the command register is written. This will start the IO transfer. The REG_IOM_CMD register contains the command itself, along with other fields used in the command, such as channel number, offset counts and transfer size.
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Apollo3 Blue Datasheet IOM PAUSE EXAMPLE GPIO Software MSPI BLE Other IOM EXTERNAL EVENT/ WRITE TO REMOVE PAUSE CONDITION TIME CQ FETCH AND WRITE 1 CQ FETCH AND WRITE 2 Write which causes PAUSE event CQ FETCH AND WRITE 4 CQ PAUSED CQ FETCH AND WRITE 10 (CQEN OFF/DISABLE) ADDRESS 1 WRITE DATA 1 ADDRESS 2 WRITE DATA 2 ADDRESS 3 WRITE DATA 3 CQ BUFFER ADDRESS 4 WRITE DATA 4 ADDRESS 10 WRITE DATA 10 Figure 20.
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IOM2MSPI_0 IOM2MSPI_1 IOM CQFLAG OUT 7 6 5 4 3 2 1 0 Apollo3 Blue Datasheet 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REG_IOM_CQFLAGS OR PAUSE CQ MSPI 0 MSPI 1 MSPI 0 MSPI 1 GPIO IOM BLE REG_IOM_CQPAUSEEN CURIDX CURIDX >= ENDIDX? ENDIDX Figure 21. CQ Pause Bit Fetching The first 8 pause sources (bits 7:0) are register bits which are directly writable via the MCU or through the CQ. These first 8 locations are called SW Flags.
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Apollo3 Blue Datasheet - For multiple commands using DMA, the DMAEN must be reset after the command is done and before the DMA registers are set for the next transaction. - It is possible for the CQ to write the REG_IOM_CQADDR register during the CQ operation. The new address will take effect on the next fetch and allows the CQ to be relocated or looped. - When starting the CQ operation, 1 doublet will be fetched regardless of the state of the pause status and bits.
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Apollo3 Blue Datasheet frequency of 1.2 kHz. If TOTPER division is enabled by REG_IOMSTRn_CLKCFG_DIVEN, the length of the low period of the clock is specified by REG_IOMSTRn_CLKCFG_LOWPER + 1. Otherwise, the clock will have a 50% duty cycle. 48 MHz 24 MHz ... DIV3 CLKCTR 768 kHz LOWCMP FSEL DIV3 Set IFC_CLK CLKFF TOTCMP Clr DIVEN Figure 22. I2C/SPI Master Clock Generation 8.
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Apollo3 Blue Datasheet error interrupt. If software attempts to write the Command Register when another Command is underway or write the CMD register with a write command when the FIFO is empty (unless the LENGTH field in the CMD is zero), the Master will generate an ICMD error interrupt. 8.6 FIFO The I2C/SPI Master includes a 64-byte local RAM (LRAM) for data transfers. The LRAM functions as a FIFO. Only 32-bit word accesses are supported to the FIFO from the CPU.
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Apollo3 Blue Datasheet 8.7.2 Start Data Transfer A change in the state of SDA from high to low, while SCL is high, defines the START condition. A START condition which occurs after a previous START, but before a STOP, is called a RESTART condition, and functions exactly like a normal STOP followed by a normal START. 8.7.3 Stop Data Transfer A change in the state of SDA from low to high, while SCL is high, defines the STOP condition. 8.7.
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Apollo3 Blue Datasheet 1 SDA 1 0 1 0 0 R W 0 A SCL Figure 25. I2C 7-bit Address Operation Figure 26 shows the operation with which the master addresses the Apollo3 Blue MCU with a 10-bit address configured at 0x536. After the START condition, the 10-bit preamble 0b11110 is transmitted first, followed by the upper two bits of the ADDRESS field and the eighth bit indicating a write (RW = 0) or a read (RW = 1) operation.
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Apollo3 Blue Datasheet Byte N SDA Addr W A Offset A 7 Byte N+1 0 A 7 Byte N+2 0 A 7 0 A SCL Figure 28. I2C Normal Write Operation 8.7.9 I2C Normal Read Operation If a Normal Read operation is selected in the OPER field of the Command, the I2C/SPI Master first executes an Offset Address Transmission to load the Address Pointer of the slave with the desired Offset Address.
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Apollo3 Blue Datasheet important for slave devices which do not support an Address Pointer architecture. For devices which do include an Address Pointer, multiple Raw Reads may be executed after a Normal Read to access subsequent registers as the Address Pointer increments, without having to execute the Offset Address Transmission for each access. Byte N SDA Addr R A 7 Byte N+1 0 A 7 0 N SCL Figure 31. I2C Raw Read Operation 8.7.
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Apollo3 Blue Datasheet SPI operations may transfer up to 4095 bytes in a single transfer, as the TSIZE field in the CMD register provides a 12-bit length specification. 8.8.2 SPI Slave Addressing In SPI mode, the Command specifies the slave channel to be used in theCMDSEL field. The I2C/SPI Master supports up to four slaves, each of which has its own nCE signal which can be configured on an IO pin. Additional slaves may be supported using GPIO pins and external decoding. 8.8.
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Apollo3 Blue Datasheet Offset Address MOSI X R 6 5 4 3 2 Data Byte N 1 Data Byte N+1 0 X MISO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 SCK nCE Figure 33. SPI Normal Read Operation As with a Normal Write, the Offset Address byte including the RW bit is taken from the offset field(s) of CMD. If the slave expects an RW bit, the msb of the offset must be set accordingly. This allows reads from devices which have different formats for the address byte. 8.8.
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Apollo3 Blue Datasheet 8.8.7 SPI 3-wire Mode In 3-wire mode, the MOSI and MISO lines are shared on a single pin. As described in the previous sections, the MISO and MOSI lines are not driven at the same time, so 3-wire mode is equivalent to simply tying them together external to the Apollo3 Blue MCU. 3-wire mode is configured by selecting the MxWIR3 alternative (x = 0 to 5 selecting the I2C/SPI Master) in the GPIO Pad Multiplexor rather than the MxMOSI and MxMISO alternatives.
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Apollo3 Blue Datasheet nCE CPOL=0 SCK CPOL=1 SCK MOSI X 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 X MISO X 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 X CPHA=0 MOSI X 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 X MISO X 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 X CPHA=1 Figure 37. SPI CPOL and CPHA If CPOL is 0, the clock SCK is normally low and positive pulses are generated during transfers.
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Apollo3 Blue Datasheet Command is executed with an offset of 10 and a length of 6. This Command will be executed 8 times, each time bursting 6 bytes of data from registers 10-15 in the peripheral to the I2C/SPI Master FIFO. When CMDCMP is received the FIFO in the I2C/SPI Master will contain 48 bytes of data. The bytes of data are packed in the FIFO – there are no gaps between samples. 8.
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Apollo3 Blue Datasheet Flow control may be asserted either prior to the first byte transfer, which will delay the start of SCK, or within each byte transferred, which will pause SCK at the end of that byte. The examples below assume that WTFCPOL or RDFCPOL are set to 0. Figure 38 shows the operation of flow control at the beginning of a write transfer or a normal read transfer which begins with an offset byte write.
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Apollo3 Blue Datasheet Window SCK nCE MISO/IRQ MOSI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 Figure 40. Flow Control in the Middle of a Write Transfer Figure 41 shows the operation of flow control in the middle of a read transfer. IRQ must be deasserted after the leading edge of SCK on the first bit of the byte (labelled 7) and before the falling edge of the 7th bit of the byte (labelled 1) in order to insure that SCK stops at the end of the byte.
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Apollo3 Blue Datasheet cannot be accessed if IFCEN is 0, although all of the other registers are accessible. When the module is not in use, the field should also be kept at 0 to minimize power. This is important even if IFCEN is a 0. 8.
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Apollo3 Blue Datasheet 8.15.
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Apollo3 Blue Datasheet Table 395: IOM Register Map Address(s) DS-A3-0p9p1 Register Name Description 0x50004204 0x50005204 0x50006204 0x50007204 0x50008204 0x50009204 INTSTAT IO Master Interrupts: Status 0x50004208 0x50005208 0x50006208 0x50007208 0x50008208 0x50009208 INTCLR IO Master Interrupts: Clear 0x5000420C 0x5000520C 0x5000620C 0x5000720C 0x5000820C 0x5000920C INTSET IO Master Interrupts: Set 0x50004210 0x50005210 0x50006210 0x50007210 0x50008210 0x50009210 CLKCFG I/O Clock Configurat
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Apollo3 Blue Datasheet Table 395: IOM Register Map Address(s) DS-A3-0p9p1 Register Name Description 0x50004240 0x50005240 0x50006240 0x50007240 0x50008240 0x50009240 DMATRIGEN DMA Trigger Enable Register 0x50004244 0x50005244 0x50006244 0x50007244 0x50008244 0x50009244 DMATRIGSTAT DMA Trigger Status Register 0x50004280 0x50005280 0x50006280 0x50007280 0x50008280 0x50009280 DMACFG DMA Configuration Register 0x50004288 0x50005288 0x50006288 0x50007288 0x50008288 0x50009288 DMATOTCOUNT DMA Tota
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Apollo3 Blue Datasheet Table 395: IOM Register Map Address(s) Description 0x500042A0 0x500052A0 0x500062A0 0x500072A0 0x500082A0 0x500092A0 CQFLAGS Command Queue Flag Register 0x500042A4 0x500052A4 0x500062A4 0x500072A4 0x500082A4 0x500092A4 CQSETCLEAR Command Queue Flag Set/Clear Register 0x500042A8 0x500052A8 0x500062A8 0x500072A8 0x500082A8 0x500092A8 CQPAUSEEN Command Queue Pause Enable Register CQCURIDX IOM Command Queue current index value .
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Apollo3 Blue Datasheet Table 395: IOM Register Map Address(s) 0x50004410 0x50005410 0x50006410 0x50007410 0x50008410 0x50009410 DS-A3-0p9p1 Register Name IOMDBG Description IOM Debug Register Page 287 of 909 2019 Ambiq Micro, Inc. All rights reserved.
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Apollo3 Blue Datasheet 8.15.2 IOM Registers 8.15.2.1 FIFO Register FIFO Access Port OFFSET: 0x00000000 INSTANCE 0 ADDRESS: 0x50004000 INSTANCE 1 ADDRESS: 0x50005000 INSTANCE 2 ADDRESS: 0x50006000 INSTANCE 3 ADDRESS: 0x50007000 INSTANCE 4 ADDRESS: 0x50008000 INSTANCE 5 ADDRESS: 0x50009000 Provides direct random access to both input and output fifos. The state of the FIFO is not distured by reading these locations (ie no POP will be done).
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Apollo3 Blue Datasheet Table 398: FIFOPTR Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 FIFO1REM 2 0 1 9 1 8 1 7 1 6 1 5 1 4 FIFO1SIZ 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 FIFO0REM 0 4 0 3 0 2 0 1 0 0 FIFO0SIZ Table 399: FIFOPTR Register Bits Bit Name Reset RW Description 31:24 FIFO1REM 0x0 RO The number of remaining data bytes slots currently in FIFO 1 (written by interface, read by MCU) 23:16 FIFO1SIZ 0x0 RO The number of valid data bytes currently i
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Apollo3 Blue Datasheet Table 401: FIFOTHR Register Bits Bit Name Reset RW 31:14 RSVD 0x0 RO 13:8 FIFOWTHR 0x0 RW 7:6 RSVD 0x0 RO 5:0 FIFORTHR 0x0 RW Description RESERVED FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes, as indicated by the FIFO0REM field.
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Apollo3 Blue Datasheet Table 403: FIFOPOP Register Bits Bit Name 31:0 Reset FIFODOUT RW 0x0 RW Description This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0), the fifo read pointer will be advanced by one word as a result of the read. 8.15.2.
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Apollo3 Blue Datasheet INSTANCE 4 ADDRESS: 0x50008110 INSTANCE 5 ADDRESS: 0x50009110 Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register, and also controls to reset the internal pointers of the FIFOs.
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Apollo3 Blue Datasheet Table 408: FIFOLOC Register 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 RSVD 0 6 0 5 0 4 0 3 0 2 0 1 0 0 FIFOWPTR 3 0 FIFORPTR 3 1 RSVD Table 409: FIFOLOC Register Bits Bit Name Reset RW 31:12 RSVD 0x0 RO 11:8 FIFORPTR 0x0 RW 7:4 RSVD 0x0 RO 3:0 FIFOWPTR 0x0 RW Description Reserved Current FIFO read pointer.
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Apollo3 Blue Datasheet Table 411: INTEN Register Bits Bit Name Reset RW 31:15 RSVD 0x0 RO 14 CQERR 0x0 RW 13 12 CQUPD CQPAUSED 0x0 0x0 RW RO Description RESERVED Error during command queue operations CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.
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Apollo3 Blue Datasheet Table 411: INTEN Register Bits Bit Name 0 Reset CMDCMP RW 0x0 RW Description Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed. 8.15.2.
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Apollo3 Blue Datasheet Table 413: INTSTAT Register Bits Bit Name Reset RW Description DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified. 11 DERR 0x0 RW 10 DCMP 0x0 RW DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state 9 ARB 0x0 RW Arbitration loss interrupt.
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Apollo3 Blue Datasheet INSTANCE 5 ADDRESS: 0x50009208 Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
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Apollo3 Blue Datasheet Table 415: INTCLR Register Bits Bit Name Reset RW Description 5 IACC 0x0 RW illegal FIFO access interrupt. Asserted when there is a overflow or underflow event 4 NAK 0x0 RW I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus. 3 FOVFL 0x0 RW Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop. 2 FUNDFL 0x0 RW Read FIFO Underflow interrupt.
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Apollo3 Blue Datasheet Table 417: INTSET Register Bits Bit Name Reset RW 31:15 RSVD 0x0 RO 14 CQERR 0x0 RW 13 12 CQUPD CQPAUSED 0x0 0x0 RW RO Description RESERVED Error during command queue operations CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.
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Apollo3 Blue Datasheet Table 417: INTSET Register Bits Bit Name 0 Reset CMDCMP RW 0x0 RW Description Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed. 8.15.2.
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Apollo3 Blue Datasheet Table 419: CLKCFG Register Bits Bit Name Reset RW Description Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider, and if enabled 11 DIV3 0x0 RW DIS = 0x0 - Select divide by 1. EN = 0x1 - Select divide by 3. Select the input clock frequency. 10:8 FSEL 0x0 RW 7:1 RSVD 0x0 RO 0 IOCLKEN 0x0 RW MIN_PWR = 0x0 - Selects the minimum power clock. This setting should be used whenever the IOM is not active.
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Apollo3 Blue Datasheet Table 421: SUBMODCTRL Register Bits Bit Name Reset RW 31:8 RSRVD 0x0 RO Description Reserved Submodule 0 module type. This is the I2C Master interface 7:5 SMOD1TYPE 0x1 RO 4 SMOD1EN 0x0 RW MSPI = 0x0 - SPI Master submodule I2C_MASTER = 0x1 - MI2C submodule SSPI = 0x2 - SPI Slave submodule SI2C = 0x3 - I2C Slave submodule NA = 0x7 - NOT INSTALLED Submodule 1 enable (1) or disable (0) Submodule 0 module type. This is the SPI Master interface.
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Apollo3 Blue Datasheet Table 423: CMD Register Bits Bit Name Reset RW Description 31:24 OFFSETLO 0x0 RW This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command. 23:22 RSRVD22 0x0 RO 21:20 CMDSEL 0x0 RW Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions 19:8 TSIZE 0x0 RW Defines the transaction size in bytes.
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Apollo3 Blue Datasheet 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 RSVD 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CE0OUT 2 8 CE1OUT 2 9 CE2OUT 3 0 CE3OUT 3 1 DCXEN Table 424: DCX Register Table 425: DCX Register Bits Bit Name Reset RW 31:5 RSVD 0x0 RO 4 DCXEN 0x0 RW Description RESERVED Revision A: MUST NOT be programmed! Revision B: Bit 4: DCX Signaling Enable via other CE signals.
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Apollo3 Blue Datasheet Table 426: OFFSETHI Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 RSVD 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 OFFSETHI Table 427: OFFSETHI Register Bits Bit Name Reset RW 31:16 RSVD 0x0 RO 15:0 OFFSETHI 0x0 RW Description Reserved Holds the high order 2 bytes of the 3 byte addressing/offset field to use with IO commands.
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Apollo3 Blue Datasheet Table 429: CMDSTAT Register Bits Bit Name Reset RW 31:20 RSRVD0 0x0 RO 19:8 CTSIZE 0x0 RO Description Reserved The current number of bytes still to be transferred with this command. This field will count down to zero. The current status of the command execution.
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Apollo3 Blue Datasheet Table 431: DMATRIGEN Register Bits Bit Name Reset RW 31:2 RSVD 0x0 RO 1 DTHREN 0 0x0 DCMDCMPEN RW 0x0 RW Description RESERVED. Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes), the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO, and will transfer (WTHR/4) number of words Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed.
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Apollo3 Blue Datasheet Table 433: DMATRIGSTAT Register Bits Bit Name Reset RW Description DMA triggered when DCMDCMP = 0, and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is 2 DTOTCMP 0x0 RO 1 DTHR 0x0 RO Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA.
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Apollo3 Blue Datasheet Table 435: DMACFG Register Bits Bit Name Reset RW Description Sets the Priority of the DMA request 8 DMAPRI 0x0 RW 7:2 RSVD 0x0 RO LOW = 0x0 - Low Priority (service as best effort) HIGH = 0x1 - High Priority (service immediately) RESERVED. Direction 1 DMADIR 0x0 RW P2M = 0x0 - Peripheral to Memory (SRAM) transaction. To be set when doing IOM read operations, ie reading data from external devices. M2P = 0x1 - Memory to Peripheral transaction.
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Apollo3 Blue Datasheet Table 437: DMATOTCOUNT Register Bits Bit Name 11:0 Reset TOTCOUNT RW 0x0 RW Description Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA. 8.15.2.
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Apollo3 Blue Datasheet Table 439: DMATARGADDR Register Bits Bit Name 19:0 Reset TARGADDR RW 0x0 RW Description Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment, and does not have to be word aligned. In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written. 8.15.2.
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Apollo3 Blue Datasheet 8.15.2.24CQCFG Register Command Queue Configuration Register OFFSET: 0x00000294 INSTANCE 0 ADDRESS: 0x50004294 INSTANCE 1 ADDRESS: 0x50005294 INSTANCE 2 ADDRESS: 0x50006294 INSTANCE 3 ADDRESS: 0x50007294 INSTANCE 4 ADDRESS: 0x50008294 INSTANCE 5 ADDRESS: 0x50009294 Controls parameters and options for execution of the command queue operation. To enable command queue, create this in memory, set the address, and enable it with a write to CQEN.
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Apollo3 Blue Datasheet INSTANCE 4 ADDRESS: 0x50008298 INSTANCE 5 ADDRESS: 0x50009298 The SRAM address in this register is fetched on next execution of the CQ operation. This register is updated as the CQ operation progresses, and is the live version of the register. The register can also be written by the Command Queue operation itself, allowing the relocation of successive CQ fetches. In this case, the new CQ address will be used for the next CQ address/data fetch.
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Apollo3 Blue Datasheet 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 RSVD 0 2 0 1 0 0 CQTIP 3 0 CQPAUSED 3 1 CQERR Table 446: CQSTAT Register Table 447: CQSTAT Register Bits Bit Name Reset RW 31:3 RSVD 0x0 RO 2 CQERR 0x0 RW 1 CQPAUSED 0x0 RO 0 CQTIP 0x0 RO Description RESERVED. Command queue processing Error.
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Apollo3 Blue Datasheet Table 449: CQFLAGS Register Bits Bit Name Reset RW 31:16 CQIRQMASK 0x0 RW 15:0 CQFLAGS 0x0 RO Description Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt, if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status. 8.15.2.
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Apollo3 Blue Datasheet 8.15.2.29CQPAUSEEN Register Command Queue Pause Enable Register OFFSET: 0x000002A8 INSTANCE 0 ADDRESS: 0x500042A8 INSTANCE 1 ADDRESS: 0x500052A8 INSTANCE 2 ADDRESS: 0x500062A8 INSTANCE 3 ADDRESS: 0x500072A8 INSTANCE 4 ADDRESS: 0x500082A8 INSTANCE 5 ADDRESS: 0x500092A8 Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1', CQ processing will halt until either value is changed to '0'.
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Apollo3 Blue Datasheet Table 453: CQPAUSEEN Register Bits Bit Name Reset RW Description Enables the specified event to pause command processing when active 15:0 CQPEN 0x0 RW IDXEQ = 0x8000 - Pauses the command queue when the current index matches the last index BLEXOREN = 0x4000 - Pause command queue when input BLE bit XORed with SWFLAG4 is '1' IOMXOREN = 0x2000 - Pause command queue when input IOM bit XORed with SWFLAG3 is '1' GPIOXOREN = 0x1000 - Pause command queue when input GPIO irq_bit XORed
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Apollo3 Blue Datasheet Table 454: CQCURIDX Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 RSVD 0 5 0 4 0 3 0 2 0 1 0 0 CQCURIDX Table 455: CQCURIDX Register Bits Bit Name Reset RW 31:8 RSVD 0x0 RO 7:0 CQCURIDX 0x0 RW Description RESERVED Holds 8 bits of data that will be compared with the CQENDIX register field.
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Apollo3 Blue Datasheet Table 457: CQENDIDX Register Bits Bit Name 7:0 Reset CQENDIDX RW 0x0 RW Description Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN. 8.15.2.
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Apollo3 Blue Datasheet Table 459: STATUS Register Bits Bit Name 0 Reset ERR RW 0x0 RO Description Bit has been deprecated. Please refer to the other error indicators. This will always return 0. ERROR = 0x1 - Bit has been deprecated and will always return 0. 8.15.2.
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Apollo3 Blue Datasheet Table 461: MSPICFG Register Bits Bit Name Reset RW Description Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first. 23 SPILSB 0x0 RW MSB = 0x0 - Send and receive MSB bit first LSB = 0x1 - Send and receive LSB bit first selects the read flow control signal polarity. 22 RDFCPOL 0x0 RW HIGH = 0x0 - Flow control signal high creates flow control.
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Apollo3 Blue Datasheet 8.15.2.34MI2CCFG Register I2C Master configuration OFFSET: 0x00000400 INSTANCE 0 ADDRESS: 0x50004400 INSTANCE 1 ADDRESS: 0x50005400 INSTANCE 2 ADDRESS: 0x50006400 INSTANCE 3 ADDRESS: 0x50007400 INSTANCE 4 ADDRESS: 0x50008400 INSTANCE 5 ADDRESS: 0x50009400 Controls the configuration of the I2C bus master.
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Apollo3 Blue Datasheet Table 463: MI2CCFG Register Bits Bit Name Reset RW Description Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master, this function can be disabled to save clock cycles on I2C transactions 2 ARBEN 0x0 RW ARBEN = 0x1 - Enable multi-master bus arbitration support for this i2c master ARBDIS = 0x0 - Disable multi-master bus arbitration support for this i2c master Direction of data transmit and receive, MSB(0) or LSB(1) first.
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Apollo3 Blue Datasheet Table 465: DEVCFG Register Bits Bit Name Reset RW Description 9:0 DEVADDR 0x0 RW I2C address of the device that the Master will use to target for read/write operations. This can be either a 7b or 10b address. 8.15.2.
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Apollo3 Blue Datasheet 9. I2C/SPI Slave Module IO Mux SPI Slave Controller REGs I2C Slave Controller INTs Bus Interface FIFO Figure 42. Block diagram for the I2C/SPI Slave Module 9.1 Functional Overview The I2C/SPI Slave Module, shown in Figure 42, allows the Apollo3 Blue MCU to function as a Slave in an I2C or SPI system. The I2C/SPI Slave operates in an independent fashion, so that the Apollo3 Blue MCU may be placed in a sleep mode and still receive operations over the I/O interface.
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Apollo3 Blue Datasheet resents the start of the FIFO Area and, in so doing, defines the size of the Direct Area in 8-byte segments. Part of this area can be defined as IO Slave Read-only starting at any 8-byte segment defined by REG_IOSLAVE_FIFOCFG_ROBASE and extending through the end of the Direct Area at FIFOBASE*8-1. 2. A FIFO Area which is used to stream data from the Apollo3 Blue MCU.
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Apollo3 Blue Datasheet memory locations within the Direct Area and corresponding interrupt bit settings in the REGACCINTSTAT register. I/O writes to locations 0x0-0xF will set a corresponding interrupt flag in the REGACCINTSTAT register. These locations are typically used for specific commands to the Apollo3 Blue MCU. Note that not all flags need generate an actual interrupt, so small multi-byte commands may be transmitted in this area.
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Apollo3 Blue Datasheet Table 468: Mapping of Direct Area Access Interrupts and Corresponding REGACCINTSTAT Bits REGACCINTSTAT Bit Direct Area Offset Address 31 0x0 30 0x1 29 0x2 28 0x3 27 0x4 26 0x5 25 0x6 24 0x7 23 0x8 22 0x9 21 0xA 20 0xB 19 0xC 18 0xD 17 0xE 16 0xF 15 0x13 14 0x17 13 0x1B 12 0x1F 11 0x23 10 0x27 9 0x2B 8 0x2F 7 0x33 6 0x37 5 0x3B 4 0x3F 3 0x43 2 0x47 1 0x4B 0 0x4F The REGACCINTSTAT register provides status of the 32 indiv
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Apollo3 Blue Datasheet speed software decoding, and is therefore very useful for quickly servicing the highest priority REGACC interrupt (i.e. the one at the lowest offset address). The encoding works such that if interrupt 31 is set, PRENC will be 0. If interrupt 31 is not set and bit 30 is set, PRENC will be 1, and so on to the point where if bits 31-1 are not set and bit 0 is set PRENC will be 31. If no interrupts are set the value in PRENC is indeterminate.
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Apollo3 Blue Datasheet FIFO Read Data @ 0x7F Cur Data FIFOPTR Local FIFO FIFO Area in LRAM Decrement on FIFO Read FIFOSIZ Increment on FIFO area Write Compare FIFO Buffer in SRAM FIFO Int FIFOTHR Decrement on FIFO Read FIFOCTR Add value on write to FIFOINC Host Readable at 0x7C/0x7D Figure 44. I2C/SPI Slave Module FIFO When the host reads a byte from the FIFO, the data retrieved is pointed to by FIFOPTR, FIFOPTR is incremented and wraps around in the FIFO Area if it reaches FIFOMAX.
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Apollo3 Blue Datasheet If software desires to write the current sample to the front of the FIFO, it first checks the REG_IOSLAVE_FUPD_IOREAD status bit to ensure that there is not a Host read operation from the FIFO underway. Once IOREAD is clear, software sets the REG_IOSLAVE_FUPD_FIFOUPD bit, writes the new sample data to the front of the FIFO and modifies the FIFOPTR to point to the new data. At that point the FIFOUPD bit is cleared.
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Apollo3 Blue Datasheet writing a 1 to the IOINTCLR bit of the IOINTCTL register. This allows the Apollo3 Blue MCU to generate a software interrupt to the Host device. In addition, a FIFO underflow interrupt FUNDFL in the I2C/SPI Slave will set interrupt bit 7, and a FIFO read error interrupt FRDERR will set interrupt bit 6 of the IO interrupt status register IOINT.
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Apollo3 Blue Datasheet The following protocol has been defined: ▪ Data transfer may be initiated only when the bus is not busy. ▪ During data transfer, the data line must remain stable whenever the clock line is high. ▪ Changes in the data line while the clock line is high will be interpreted as control signals. A number of bus conditions have been defined (see Figure 45) and are described in the following sections. SDA may change Not Busy SCL SDA START SDA Stable STOP Figure 45.
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Apollo3 Blue Datasheet SCL 1 2 8 9 SDA MSB (bit 7) Bit 6 Bit 0 ACK START Figure 46. I2C Acknowledge 9.9.6 Address Operation In I2C mode, the I2C/SPI Slave supports either 7-bit or 10-bit addressing, selected by the 10BIT bit in the IOSCFG Register. Figure 47 shows the operation in 7-bit mode in which the master addresses the Apollo3 Blue MCU with a 7-bit address configured as 0xD2 in the I2CADDR field. After the START condition, the 7bit address is transmitted MSB first.
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Apollo3 Blue Datasheet Offset Address SDA 1 1 0 1 0 0 0 0 A 7 6 5 4 3 2 1 0 A SCL Figure 49. I2C Offset Address Transmission 9.9.8 Write Operation In a write operation the master transmitter transmits to the Apollo3 Blue MCU slave receiver. The Address Operation has a RW value of 0, and the second byte contains the Offset Address as in Figure 49.
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Apollo3 Blue Datasheet 9.9.10 General Address Detection The I2C/SPI Slave may be configured to detect an I2C General Address (0x00) write. If this address is detected, the first data byte written is stored in the REG_IOSLAVE_GADATA Register and the GENAD interrupt flag is set. This allows software to create the appropriate response, which is typically to reset the I2C/SPI Slave. 9.10 SPI Interface The I2C/SPI Slave includes a standard 3-wire or 4-wire SPI interface.
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Apollo3 Blue Datasheet 9.10.2 Read Operation Figure 53 shows a read operation. The address is transferred from the master to the slave just as it is in a write operation, but in this case the RW bit is a 0 indicating a read. After the transfer of the last address bit (bit 0), the I2C/SPI Slave begins driving data from the register selected by the Address Pointer onto the MISO line, bit 7 first, and the Address Pointer is incremented. The transfer continues until the master brings the nCE line high.
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Apollo3 Blue Datasheet If CPOL is 0, the clock SCK is normally low and positive pulses are generated during transfers. If CPOL is 1, SCK is normally high and negative pulses are generated during transfers. If CPHA is 0, the data on the MOSI and MISO lines is sampled on the edge corresponding to the first SCK edge after nCE goes low (i.e. the rising edge if CPOL is 0 and the falling edge if CPOL is 1). Data on MISO and MOSI is driven on the opposite edge of SCK.
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Apollo3 Blue Datasheet 9.13.
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Apollo3 Blue Datasheet 9.13.2 IOSLAVE Registers 9.13.2.
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Apollo3 Blue Datasheet Table 474: FIFOCFG Register Bits Bit Name Reset RW 31:30 RSVD 0x0 RO 29:24 ROBASE 0x20 RW 23:16 RSVD 0x0 RO 15:14 RSVD 0x0 RO 13:8 FIFOMAX 0x0 RW 7:5 RSVD 0x0 RO 4:0 FIFOBASE 0x0 RW Description RESERVED Defines the read-only area. The IO Slave read-only area is situated in LRAM at (ROBASE*8) to (FIFOBASE*8-1) RESERVED RESERVED These bits hold the maximum FIFO address in 8 byte segments. It is also the beginning of the RAM area of the LRAM.
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Apollo3 Blue Datasheet 9.13.2.
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Apollo3 Blue Datasheet Table 480: FIFOCTR Register Bits Bit Name Reset RW 9:0 FIFOCTR 0x0 RW Description Virtual FIFO byte count 9.13.2.
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Apollo3 Blue Datasheet Table 484: CFG Register Bits Bit Name Reset RW Description IOSLAVE interface enable. 31 IFCEN 0x0 RW 30:20 RSVD 0x0 RO 19:8 I2CADDR 0x0 RW 7:5 RSVD 0x0 RO DIS = 0x0 - Disable the IOSLAVE EN = 0x1 - Enable the IOSLAVE RESERVED 7-bit or 10-bit I2C device address. RESERVED This bit holds the cycle to initiate an I/O RAM read. 4 STARTRD 0x0 RW 3 RSVD 0x0 RO LATE = 0x0 - Initiate I/O RAM read late in each transferred byte.
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Apollo3 Blue Datasheet Table 486: PRENC Register Bits Bit Name Reset RW 31:5 RSVD 0x0 RO 4:0 PRENC 0x0 RO Description RESERVED These bits hold the priority encode of the REGACC interrupts. 9.13.2.
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Apollo3 Blue Datasheet Table 489: GENADD Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 RSVD 0 4 0 3 0 2 0 1 0 0 GADATA Table 490: GENADD Register Bits Bit Name Reset RW 31:8 RSVD 0x0 RO 7:0 GADATA 0x0 RO Description RESERVED The data supplied on the last General Address reference. 9.13.2.
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Apollo3 Blue Datasheet Table 492: INTEN Register Bits Bit Name Reset RW 5 IOINTW 0x0 RW 4 GENAD 0x0 RW 3 FRDERR 0x0 RW 2 FUNDFL 0x0 RW 1 FOVFL 0x0 RW 0 FSIZE 0x0 RW Description IO Write interrupt. I2C General Address interrupt. FIFO Read Error interrupt. FIFO Underflow interrupt. FIFO Overflow interrupt. FIFO Size interrupt. 9.13.2.
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Apollo3 Blue Datasheet Table 494: INTSTAT Register Bits Bit Name Reset RW 4 GENAD 0x0 RW 3 FRDERR 0x0 RW 2 FUNDFL 0x0 RW 1 FOVFL 0x0 RW 0 FSIZE 0x0 RW Description I2C General Address interrupt. FIFO Read Error interrupt. FIFO Underflow interrupt. FIFO Overflow interrupt. FIFO Size interrupt. 9.13.2.13INTCLR Register IO Slave Interrupts: Clear OFFSET: 0x00000208 INSTANCE 0 ADDRESS: 0x50000208 Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
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Apollo3 Blue Datasheet Table 496: INTCLR Register Bits Bit Name Reset RW 3 FRDERR 0x0 RW 2 FUNDFL 0x0 RW 1 FOVFL 0x0 RW 0 FSIZE 0x0 RW Description FIFO Read Error interrupt. FIFO Underflow interrupt. FIFO Overflow interrupt. FIFO Size interrupt. 9.13.2.14INTSET Register IO Slave Interrupts: Set OFFSET: 0x0000020C INSTANCE 0 ADDRESS: 0x5000020C Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
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Apollo3 Blue Datasheet Table 498: INTSET Register Bits Bit Name Reset RW 3 FRDERR 0x0 RW 2 FUNDFL 0x0 RW 1 FOVFL 0x0 RW 0 FSIZE 0x0 RW Description FIFO Read Error interrupt. FIFO Underflow interrupt. FIFO Overflow interrupt. FIFO Size interrupt. 9.13.2.15REGACCINTEN Register Register Access Interrupts: Enable OFFSET: 0x00000210 INSTANCE 0 ADDRESS: 0x50000210 Set bits in this register to allow this module to generate the corresponding interrupt.
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Apollo3 Blue Datasheet Table 502: REGACCINTSTAT Register Bits Bit Name Reset RW 31:0 REGACC 0x0 RW Description Register access interrupts. 9.13.2.17REGACCINTCLR Register Register Access Interrupts: Clear OFFSET: 0x00000218 INSTANCE 0 ADDRESS: 0x50000218 Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
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Apollo3 Blue Datasheet Table 506: REGACCINTSET Register Bits Bit Name Reset RW 31:0 REGACC 0x0 RW Description Register access interrupts. 9.14 Host Side Address Space and Register 9.14.1 Host Address Space and Registers The Host of the I/O interface can access 128 bytes in the I2C/SPI Slave in either I2C or SPI mode. Offsets 0x00 to 0x77 may be directly mapped to the Direct RAM Area. The remaining eight offset locations access hardware functions within the I2C/SPI Slave.
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Apollo3 Blue Datasheet 9.14.1.2 HOST_ISR Register Host Interrupt Status Register OFFSET: 0x79 The host uses this register to read interrupt status.
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Apollo3 Blue Datasheet Table 512: HOST_WCR Register Bits Bit Name Reset RW Description 7 FUNDFLWC 0x0 WO Writing a 1 to this bit will clear the pending interrupt status bit FUNDFLSTAT 6 RDERRWC 0x0 WO Writing a 1 to this bit will clear the pending interrupt status bit RDERRSTAT 5 SWINT5WC 0x0 WO Writing a 1 to this bit will clear the pending interrupt status bit SWINT5STAT 4 SWINT4WC 0x0 WO Writing a 1 to this bit will clear the pending interrupt status bit SWINT4STAT 3 SWINT3WC
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Apollo3 Blue Datasheet 9.14.1.5 FIFOCTRLO Register FIFOCTR Low Byte OFFSET: 0x7C This register allows the host to read the lower eight bits of the FIFOCTR register. Table 515: FIFOCTRLO Register 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 FIFOCTRLO Table 516: FIFOCTRLO Register Bits Bit Name Reset RW 7:0 FIFOCTRLO 0x0 RO Description Reads the lower eight bits of FIFOCTR 9.14.1.
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Apollo3 Blue Datasheet 9.14.1.7 FIFO Register FIFO Read Data OFFSET: 0x7F Read this register for FIFO data. Table 519: FIFO Register 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 FIFO Table 520: FIFO Register Bits Bit Name Reset RW 7:0 FIFO 0x0 RO DS-A3-0p9p1 Description Reads the top byte of the FIFO Page 356 of 909 2019 Ambiq Micro, Inc. All rights reserved.
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Apollo3 Blue Datasheet 10. PDM/I2S Module I2S Controller REGs Decimator IO Mux Left PDM-PCM Conversion Right PDM-PCM Conversion INTs Bus Interface FIFO Figure 55. Block Diagram for PDM Module 10.1 Features The PDM module provides support for low power Pulse-Density Modulated (PDM) to Pulse-Code Modulated (PCM) conversion and optional I2S slave interface for external host processor communication.
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Apollo3 Blue Datasheet frequency PDM clock is generated to the microphone (requires digital microphone that supports low power operation). Once a keyword is detected, the MCU generates a wake event to enter normal mode. In normal mode, higher PDM frequencies are supported to process audio/voice as needed for voice recording, voice calls, etc. 10.2.
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Apollo3 Blue Datasheet the clock of the internal PDM logic, and therefore the lowest acceptable frequency should be selected to minimize power. The PDM logic includes separately clocked sections for each of the left and right channels. The input clock is divided by 1, 2, 3 or 4 as selected by the PCFG_MCLKDIV field to produce the PDM_CLKO output.
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Apollo3 Blue Datasheet sufficient. However, for voice recording/playback scenarios, this could manifest as pitch/noise problems. In a scenario where the Apollo3 Blue MCU is used for voice/keyword detect, upon detection, the Apollo3 Blue MCU can generate notification to the external host. The external host can then send a command to the Apollo3 Blue MCU to switch clock source.
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Apollo3 Blue Datasheet Table 522: PDM Operating Modes and Data Formats Mode CHSET PCMPACK LRSWAP Mono Left Unpacked 01 0 N/A Mono Right Unpacked 10 0 N/A Stereo Unpacked 11 0 0 Stereo Unpacked Swapped 11 0 1 Disabled 00 N/A N/A 31 - FIFO Data Format - 0 0000 L0 0000 L1 0000 R0 0000 R1 0000 L0 0000 R0 0000 R0 0000 L0 0000 0000 0000 0000 MCLKL MCLKR En Dis Dis En En En En En Dis Dis The MCLKL and MCLKR columns indicate whether the left and right channel
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Apollo3 Blue Datasheet Port Name PGA_R[4:0] Default Description Right Channel PGA Gain: +1.5dB/step, -6dB to +40.5dB 00000 = -6 dB 00001 = -4.5 dB \u2026 11110 = +39 dB 11111 = +40.5 dB 0000 10.2.7 Low Pass Filter (LPF) The controller’s internal low pass filters attenuate the out-of-band noise at predefined bandwidth and corners. Table 524: LPF Digital Filter Parameters Parameter Min Pass band corner frequency Typ Max 0.41 Pass band ripple -1 Stop band corner frequency 0.
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Apollo3 Blue Datasheet Figure 59. I2S Interface Data Format Timing 1/Fs Left Channel (Low) Right Channel (High) I2S_WDCLK I2S_BCLK I2S_DAT 1 2 MSB n‐1 n 1 LSB MSB 2 n‐1 n 1 LSB MSB 2 Figure 60. I2S Interface Setup and Hold Timing Diagram I2S_WDCLK IH‐LRC IS‐LRC I2S_BCLK I2S_DAT TD_DAT 10.4 PDM Registers PDM Audio INSTANCE 0 BASE ADDRESS:0x50011000 DS-A3-0p9p1 Page 363 of 909 2019 Ambiq Micro, Inc. All rights reserved.
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Apollo3 Blue Datasheet 10.4.
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Apollo3 Blue Datasheet 10.4.2 PDM Registers 10.4.2.
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Apollo3 Blue Datasheet Table 527: PCFG Register Bits Bit Name Reset RW Description Right channel PGA gain. 30:26 DS-A3-0p9p1 PGARIGHT 0x0 RW P405DB = 0x1F - 40.5 db gain. P390DB = 0x1E - 39.0 db gain. P375DB = 0x1D - 37.5 db gain. P360DB = 0x1C - 36.0 db gain. P345DB = 0x1B - 34.5 db gain. P330DB = 0x1A - 33.0 db gain. P315DB = 0x19 - 31.5 db gain. P300DB = 0x18 - 30.0 db gain. P285DB = 0x17 - 28.5 db gain. P270DB = 0x16 - 27.0 db gain. P255DB = 0x15 - 25.5 db gain. P240DB = 0x14 - 24.0 db gain.
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Apollo3 Blue Datasheet Table 527: PCFG Register Bits Bit Name Reset RW Description Left channel PGA gain. 25:21 PGALEFT 0x0 RW 20:19 RSVD 0x0 RO P405DB = 0x1F - 40.5 db gain. P390DB = 0x1E - 39.0 db gain. P375DB = 0x1D - 37.5 db gain. P360DB = 0x1C - 36.0 db gain. P345DB = 0x1B - 34.5 db gain. P330DB = 0x1A - 33.0 db gain. P315DB = 0x19 - 31.5 db gain. P300DB = 0x18 - 30.0 db gain. P285DB = 0x17 - 28.5 db gain. P270DB = 0x16 - 27.0 db gain. P255DB = 0x15 - 25.5 db gain. P240DB = 0x14 - 24.
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Apollo3 Blue Datasheet Table 527: PCFG Register Bits Bit Name Reset RW Description Data Streaming Control. 0 PDMCOREEN 0x1 RW EN = 0x1 - Enable Data Streaming. DIS = 0x0 - Disable Data Streaming. 10.4.2.
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Apollo3 Blue Datasheet Table 529: VCFG Register Bits Bit Name Reset RW 25:21 RSVD 0x0 RO Description This bitfield is reserved for future use. I2S interface enable. 20 I2SEN 0x0 RW DIS = 0x0 - Disable I2S interface. EN = 0x1 - Enable I2S interface. I2S BCLK input inversion. 19 BCLKINV 0x0 RW 18 RSVD 0x0 RO INV = 0x0 - BCLK inverted. NORM = 0x1 - BCLK not inverted. This bitfield is reserved for future use. PDM clock sampling delay. 17 DMICKDEL 0x0 RW 0CYC = 0x0 - No delay.
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Apollo3 Blue Datasheet Table 530: VOICESTAT Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 RSVD 0 3 0 2 0 1 0 0 0 1 0 0 FIFOCNT Table 531: VOICESTAT Register Bits Bit Name Reset RW 31:6 RSVD 0x0 RO 5:0 FIFOCNT 0x0 RO Description This bitfield is reserved for future use. Valid 32-bit entries currently in the FIFO. 10.4.2.
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Apollo3 Blue Datasheet Table 534: FIFOFLUSH Register 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 FIFOFLUSH 3 1 RSVD Table 535: FIFOFLUSH Register Bits Bit Name Reset RW 31:1 RSVD 0x0 RO 0 FIFOFLUSH 0x0 WO Description This bitfield is reserved for future use. FIFO FLUSH. 10.4.2.
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Apollo3 Blue Datasheet INSTANCE 0 ADDRESS: 0x50011200 Set bits in this register to allow this module to generate the corresponding interrupt.
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Apollo3 Blue Datasheet Table 541: INTSTAT Register Bits Bit Name Reset RW 31:5 RSVD 0x0 RO 4 DERR 0x0 RW 3 DCMP 0x0 RW 2 UNDFL 0x0 RW 1 OVF 0x0 RW 0 THR 0x0 RW Description RESERVED DMA Error receieved DMA completed a transfer This is the FIFO underflow interrupt. This is the FIFO overflow interrupt. This is the FIFO threshold interrupt. 10.4.2.
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Apollo3 Blue Datasheet Table 543: INTCLR Register Bits Bit Name Reset RW 0 THR 0x0 RW Description This is the FIFO threshold interrupt. 10.4.2.10INTSET Register IO Master Interrupts: Set OFFSET: 0x0000020C INSTANCE 0 ADDRESS: 0x5001120C Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
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Apollo3 Blue Datasheet 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 RSVD 0 1 0 0 DTHR 3 1 DTHR90 Table 546: DMATRIGEN Register Table 547: DMATRIGEN Register Bits Bit Name Reset RW Description 31:2 RSVD 0x0 RO 1 DTHR90 0x0 RW Trigger DMA at FIFO 90 percent full.
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Apollo3 Blue Datasheet Table 549: DMATRIGSTAT Register Bits Bit Name Reset RW 0 DTHRSTAT 0x0 RO Description Triggered DMA from FIFO reaching threshold 10.4.2.
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Apollo3 Blue Datasheet 10.4.2.14DMATOTCOUNT Register DMA Total Transfer Count OFFSET: 0x00000288 INSTANCE 0 ADDRESS: 0x50011288 DMA Total Transfer Count Table 552: DMATOTCOUNT Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 RSVD 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 TOTCOUNT Table 553: DMATOTCOUNT Register Bits Bit Name Reset RW 31:20 RSVD 0x0 RO 19:0 TOTCOUNT 0x0 RW Description RESERVED. Total Transfer Count.
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Apollo3 Blue Datasheet Table 555: DMATARGADDR Register Bits Bit Name 19:0 Reset LTARGADDR RW 0x0 RW Description DMA Target Address. This register is not updated with the current address of the DMA, but will remain static with the original address during the DMA transfer. 10.4.2.
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Apollo3 Blue Datasheet 11. GPIO and Pad Configuration Module GPIO REGs IO Pads Pad Muxes Config Registers Bus Interface Controller IO Figure 61. Block diagram for the General Purpose I/O (GPIO) Module 11.1 Functional Overview The General Purpose I/O and Pad Configuration (GPIO) Module, shown in Figure 61, controls connections to up to 50 digital/analog pads.
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Apollo3 Blue Datasheet Table 558: Drive Strength Control Bits ALTPADCFGy_ PADn_DS1 PADREGy_ PADnSTRNG Nominal Drive Strength (mA) 0 0 2 0 1 4 1 0 8 1 1 12 For all pads except for pad 20, REG_GPIO_PADREGy_PADnPULL bit enables a weak pull-up on the pad when set to one. For pad 20, the REG_GPIO_PADREGy_PAD20PULL bit enables a weak pull-down on the pad when set to one.
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Apollo3 Blue Datasheet Table 559: Apollo3 Blue MCU Pad Function Mapping PADnFNCSEL Pad 0 1 2 3 4 CSP PKG 5 6 7 0 SLSCL SLSCK CLKOUT GPIO00 MSPI4 NCE0 X 1 SLSDAWIR3 SLMOSI UART0TX GPIO01 MSPI5 NCE1 X 2 UART1RX SLMISO UART0RX GPIO02 MSPI6 NCE2 X 3 UA0RTS SLnCE NCE3 GPIO03 MSPI7 TRIG1 I2SWCLK X 4 UA0CTS SLINT NCE4 GPIO04 UART1RX CT17 MSPI2 X 5 M0SCL M0SCK UA0RTS GPIO05 - CT8 X 6 M0SDAWIR3 M0MISO UA0CTS GPIO06 CT10 I2SDAT X 7 NCE7 M0MOSI CLK
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Apollo3 Blue Datasheet Table 561: Pad Function Color and Symbol Code Color/ Symbol Function Pad Type ADC Signals Analog or Input, as indicated by [A] or [I] respectively I2C/SPI Slave Signals Input, Special or Push-pull output, as indicated by [I], [S] or [O] respectively, I2C/SPI Master 0 Signals Input, Special or Push-pull output, as indicated by [I], [S] or [O] respectively I2C/SPI Master 1 Signals Input, Special or Push-pull output, as indicated by [I], [S] or [O] respectively I2C/SPI Master
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Apollo3 Blue Datasheet Table 562: Special Pad Types Pad PADnFNCSEL Name Pad Type 1 0 SLSDAWIR3 1 5 MSPI5 Bidirectional Tri-state 2 5 MSPI6 Bidirectional Tri-state 3 5 MSPI7 Bidirectional Tri-state 4 7 MSPI2 Bidirectional Tri-state 5 0 M0SCL Open Drain 6 0 M0SDAWIR3 8 0 M1SCL 9 0 M1SDAWIR3 9 4 SCCIO Bidirectional Tri-state 15 6 SWDIO Bidirectional Tri-state 18 7 SCCIO Bidirectional Tri-state 21 0 SWDIO Bidirectional Tri-state 22 6 MSPI0 Bidirectional Tr
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Apollo3 Blue Datasheet Table 564: NCE Encoding Table GPIOxOUTCFG DS-A3-0p9p1 0 1 2 3 NCE0 IOM3.2 IOM4.2 IOM5.2 IOM1.3 NCE1 IOM0.2 IOM1.2 IOM2.2 MSPI.0 NCE2 IOM3.3 IOM4.3 IOM5.3 IOM2.1 NCE3 IOM3.0 IOM4.0 IOM5.0 IOM2.0 NCE4 IOM3.1 IOM4.1 IOM5.1 IOM1.1 - - - - - - - - - - NCE7 IOM3.1 IOM4.1 IOM5.1 MSPI.0 NCE8 IOM3.0 IOM4.0 IOM5.0 IOM0.0 NCE9 IOM3.3 IOM4.3 IOM5.3 IOM2.3 NCE10 IOM3.2 IOM4.2 IOM5.2 MSPI.0 NCE11 IOM0.0 IOM1.0 IOM2.0 IOM3.
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Apollo3 Blue Datasheet 11.3 General Purpose I/O (GPIO) Functions For each pad, if the PADnFNCSEL field is set to 0x3 the pad is connected to the corresponding GPIO signal. This section describes the configuration functions specific to GPIO pads. 11.3.1 Configuring the GPIO Functions Each GPIO must be configured in the REG_GPIO_CFGy (y = A to G) Registers as an input and/or output. Note that the PADKEY Register must be set to the value 0x73 in order to write the REG_GPIO_CFGy Registers.
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Apollo3 Blue Datasheet Below describes the interrupt configuration. Table 565: Interrupt Configuration INCFG INTD Interrupt 0 0 Low -> high transition 0 1 High -> low transition 1 0 Disabled 1 1 Either low -> high or high -> low transition 11.4 Pad Connection Summary Figure 62 shows the detailed implementation of each pad. Each element will be described in detail. 11.4.
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Apollo3 Blue Datasheet VDD Mux VDD PADnFNCSEL PADnRSEL GPIOnEN PADnPULL OUTENSEL Mux PADnFNCSEL GPIOnWT GPIOnEN PAD Other Outputs GPIOnWT Other Input OtherMuxes Outputs PAD Other Input Muxes OUTDATSEL PADnSTRNG OUTDATSEL PADnSTRNG GPIOnRD AND GPIOnRD GPIOnINCFG GPIOnINCFG GPIOnINTD PADnFNCSEL =3 AND OR OR AND AND PADnINPEN PADnINPEN AND AND GPIOnINT INT GPIOnINT GPIOnINTD INT XOR XOR Analog Connection GPIOnINTD PADnFNCSEL = analog Analog Connection Figure 62.
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Apollo3 Blue Datasheet 11.4.3 Input Control The input circuitry of the pad may be disabled by clearing the PADnINPEN bit. This configuration should always be set if the pad input is not being used, as it prevents unnecessary current consumption if the pad voltage happens to float to a level between VDD and Ground. If PADnINPEN is 0, the pad will always read as a 0. If PADnINPEN is set, the pad input then goes to two places. It is driven to the selected module signal as selected in Table 559.
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Apollo3 Blue Datasheet and PAD6RSEL fields should be set to select the desired pullup resistor size as shown in Table 563. If external pullup resistors are used, PAD5PULL and PAD6PULL should be cleared. Table 566: IO Master 0 I2C Configuration Field Value PAD5FNCSEL 0 PAD6FNCSEL 0 11.5.1.2 IO Master 1 I2C Connection I2C mode of IO Master 1 uses pad 8 as SCL and pad 9 as SDA. This mode is configured by setting the PADnFNCSEL fields as shown in Table 567. The PAD8INPEN and PAD9INPEN bits must be set.
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Apollo3 Blue Datasheet PAD42RSEL and PAD43RSEL fields should be set to select the desired pullup resistor size as shown in Table 563. If external pullup resistors are used, PAD42PULL and PAD43PULL should be cleared. Table 569: IO Master 3 I2C Configuration Field Value PAD42FNCSEL 4 PAD43FNCSEL 4 11.5.1.5 IO Master 4 I2C Connection I2C mode of IO Master 4 uses pad 39 as SCL and pad 40 as SDA. This mode is configured by setting the PADnFNCSEL fields as shown in Table 570.
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Apollo3 Blue Datasheet A variety of pads may be used for up to four nCE signals to select up to four separate slaves. The nCE signals are pre-muxed into a signal group called NCE. The muxing configuration is shown in Table 564. The PADnINPEN and PADnPULL bits of any pad used for nCE should be cleared. 11.5.1.8 IO Master 1 4-wire SPI Connection Four-wire SPI mode of IO Master 1 uses pad 8 as SCK, pad 9 as MISO and pad 10 as MOSI.
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Apollo3 Blue Datasheet A variety of pads may be used for up to four nCE signals to select up to four separate slaves. The nCE signals are pre-muxed into a signal group called NCE. The muxing configuration is shown in Table 564. The PADnINPEN and PADnPULL bits of any pad used for nCE should be cleared. 11.5.1.11IO Master 4 4-wire SPI Connection Four-wire SPI mode of IO Master 4 uses pad 39 as SCK, pad 40 as MISO and pad 44 as MOSI.
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Apollo3 Blue Datasheet A variety of pads may be used for up to four nCE signals to select up to four separate slaves. The nCE signals are pre-muxed into a signal group called NCE. The muxing configuration is shown in Table 564. The PADnINPEN and PADnPULL bits of any pad used for nCE should be cleared. 11.5.1.14IO Master 1 3-wire SPI Connection Three-wire SPI mode of IO Master 1 uses pad 8 as SCK and pad 9 as MOSI/MISO. This mode is configured by setting the PADnFNCSEL fields as shown in Table 579.
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Apollo3 Blue Datasheet A variety of pads may be used for up to four nCE signals to select up to four separate slaves. The nCE signals are pre-muxed into a signal group called NCE. The muxing configuration is shown in Table 564. The PADnINPEN and PADnPULL bits of any pad used for nCE should be cleared. 11.5.1.17IO Master 4 3-wire SPI Connection Three-wire SPI mode of IO Master 4 uses pad 39 as SCK and pad 40 as MOSI/MISO. This mode is configured by setting the PADnFNCSEL fields as shown in Table 582.
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Apollo3 Blue Datasheet 11.5.2 MSPI Connection The MSPI interface has various device configurations. These are mainly handled within the MSPI controller configuration. However, there are some additional pad muxing options to provide more flexibility for system integration. These mux configurations are listed below.
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Apollo3 Blue Datasheet 11.5.3.1 IO Slave I2C Connection I2C mode of the IO Slave uses pad 0 as SCL and pad 1 as SDA. This mode is configured by setting the PADnFNCSEL fields as shown in Table 586. The PAD0INPEN and PAD1INPEN bits must be set. PAD0PULL and PAD1PULL should be cleared. Table 586: IO Slave I2C Configuration Field Value PAD0FNCSEL 0 PAD1FNCSEL 0 11.5.3.2 IO Slave 4-wire SPI Connection Four-wire SPI mode of the IO Slave uses pad 0 as SCK, pad 1 as MISO, pad 2 as MOSI and pad 3 as nCE.
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Apollo3 Blue Datasheet pad is used as an input, the PADnINPEN bit should be set, otherwise it should be cleared. The PADnPULL bit may be set if the input signal is open drain.
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Apollo3 Blue Datasheet Table 589: Counter/Timer Pad Configuration Pad (FNCSEL) ctimer output signal Output Selection (REG_CTIMER_INCFG) 0 1 2 3 4 5 6 7 PAD35 (5) CT27 Force to 0 Force to 1 B6OUT2 A1OUT B6OUT B2OUT2 A6OUT2 A7OUT2 PAD37 (7) CT29 Force to 0 Force to 1 B5OUT2 A1OUT A7OUT A3OUT2 A6OUT2 A7OUT2 PAD39 (2) CT25 Force to 0 Force to 1 B4OUT2 B2OUT A6OUT A2OUT2 A6OUT2 A7OUT2 PAD42 (2) CT16 Force to 0 Force to 1 A4OUT A0OUT A0OUT2 B3OUT2 A6OUT2 A7OUT2 P
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Apollo3 Blue Datasheet Table 590: UART0 TX Configuration Field Value Pad PAD1FNCSEL 2 1 PAD7FNCSEL 5 7 PAD16FNCSEL 6 16 PAD20FNCSEL 4 20 PAD22FNCSEL 0 22 PAD26FNCSEL 6 26 PAD28FNCSEL 6 28 PAD30FNCSEL 4 30 PAD39FNCSEL 0 39 PAD41FNCSEL 6 41 PAD44FNCSEL 6 44 PAD48FNCSEL 0 48 Table 591: UART0 RX Configuration Field Value Pad PAD2FNCSEL 2 2 PAD11FNCSEL 6 11 PAD17FNCSEL 6 17 PAD21FNCSEL 4 21 PAD23FNCSEL 0 23 PAD27FNCSEL 0 27 PAD29FNCSEL 6 29 PAD31FNC
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Apollo3 Blue Datasheet which must have the corresponding PADnINPEN bit set and should have the corresponding PADnPULL bit clear.
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Apollo3 Blue Datasheet Table 594: UART1 TX Configuration Field Value Pad PAD8FNCSEL 6 8 PAD10FNCSEL 0 10 PAD12FNCSEL 7 12 PAD14FNCSEL 2 14 PAD18FNCSEL 6 18 PAD20FNCSEL 5 20 PAD24FNCSEL 0 24 PAD35FNCSEL 2 35 PAD37FNCSEL 5 37 PAD39FNCSEL 1 39 PAD42FNCSEL 0 42 PAD47FNCSEL 6 47 Table 595: UART1 RX Configuration Field Value Pad PAD2FNCSEL 0 2 PAD4FNCSEL 5 4 PAD9FNCSEL 6 9 PAD13FNCSEL 7 13 PAD15FNCSEL 2 15 PAD19FNCSEL 6 19 PAD21FNCSEL 5 21 PAD25FNCSE
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Apollo3 Blue Datasheet which must have the corresponding PADnINPEN bit set and should have the corresponding PADnPULL bit clear.
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Apollo3 Blue Datasheet Table 598: PDM CLK Configuration Field Value Pad PAD10FNCSEL 4 10 PAD12FNCSEL 5 12 PAD14FNCSEL 4 14 PAD22FNCSEL 4 22 PAD37FNCSEL 6 37 PAD46FNCSEL 5 46 Table 599: PDM DATA Configuration Field Value Pad PAD11FNCSEL 7 11 PAD15FNCSEL 4 15 PAD29FNCSEL 7 29 PAD34FNCSEL 7 34 PAD36FNCSEL 7 36 PAD45FNCSEL 5 45 11.5.6.2 I2S Connections The I2S BCLK, WCLK and DAT signalsmay each be connected to several pads.
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Apollo3 Blue Datasheet Table 602: I2S DAT Configuration Field Value Pad PAD6FNCSEL 7 6 PAD30FNCSEL 7 30 PAD35FNCSEL 4 35 PAD45FNCSEL 4 45 11.5.7 Implementing Secure Card Connections The Secure Card signals can be connected to a variety of pads. Table 603 shows the connections for Secure Card CLK (SCCCLK), which should have the corresponding PADnINPEN and PADnPULL bits clear.
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Apollo3 Blue Datasheet 11.5.9 Implementing CLKOUT Connections The flexible clock output of the Clock Generator module, CLKOUT, may be configured on several pads as shown in . PADnINPEN and PADnPULL should be cleared in each case. Table 606: CLKOUT Configuration Field Value Pad PAD0FNCSEL 2 0 PAD7FNCSEL 2 7 11.5.10Implementing 32kHz CLKOUT Connections In addition to the CLKOUT mux output, there is also a dedicated 32 kHz clock output.
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Apollo3 Blue Datasheet Table 608: ADC Analog Input Configuration Field Value Input Pad PAD12FNCSEL 0 ADCD0P/ SE9 12 PAD14FNCSEL 0 ADCD1P 14 PAD15FNCSEL 0 ADCD1M 15 I Table 609: ADC Trigger Input Configuration Field Value Input Pad PAD7FNCSEL 4 TRIG0 7 PAD16FNCSEL 2 TRIG0 16 PAD40FNCSEL 2 TRIG0 40 PAD3FNCSEL 6 TRIG1 3 PAD17FNCSEL 2 TRIG1 17 PAD36FNCSEL 0 TRIG1 36 PAD37FNCSEL 0 TRIG2 37 PAD38FNCSEL 0 TRIG3 38 11.5.
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Apollo3 Blue Datasheet Table 611: Voltage Comparator Input Configuration Field Value Input Pad PAD18FNCSEL 0 CMPIN1 18 11.5.13Implementing the Software Debug Port Connections The software debug clock (SWDCK) and data (SWDIO) must be connected on pads 20 and 21 respectively. PAD20FNCSEL and PAD21FNCSEL must be set to 0, PAD20INPEN and PAD21INPEN must be set, and PAD20PULL and PAD21PULL must be set, which results in a default state of SWDCK low and SWDIO high.
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Apollo3 Blue Datasheet 11.6.1 Register Memory Map Table 613: FASTGPIO Register Map Address(s) DS-A3-0p9p1 Register Name Description 0x40011000 BBVALUE Control Register 0x40011004 BBSETCLEAR Set/Clear Register 0x40011008 BBINPUT PIO Input Values 0x40011020 DEBUGDATA PIO Input Values 0x40011040 DEBUG PIO Input Values Page 409 of 909 2019 Ambiq Micro, Inc. All rights reserved.
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Apollo3 Blue Datasheet 11.6.2 FASTGPIO Registers 11.6.2.
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Apollo3 Blue Datasheet Table 617: BBSETCLEAR Register Bits Bit Name Reset RW 31:24 RSVD 0x0 RO 23:16 CLEAR 0x0 WO 15:8 RSVD 0x0 RO 7:0 SET 0x0 WO Description RESERVED Write 1 to Clear PIO value RESERVED Write 1 to Set PIO value (set hier priority than clear if both bit set) 11.6.2.
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Apollo3 Blue Datasheet Table 620: DEBUGDATA Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 DEBUGDATA Table 621: DEBUGDATA Register Bits Bit Name Reset RW 31:0 DEBUGDATA 0x0 RO Description Debug Data 11.6.2.
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Apollo3 Blue Datasheet This is the detailed description of the general purpose I/O (GPIO) block, as well as for the PAD multiplexor. Note that GPIO interrupt bits are edge triggered. WARNING: if an interrupt bit is cleared while the combination of polarity and input are still asserted then this bit will not set again. DS-A3-0p9p1 Page 413 of 909 2019 Ambiq Micro, Inc. All rights reserved.
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Apollo3 Blue Datasheet 11.7.
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Apollo3 Blue Datasheet Table 624: GPIO Register Map Address(s) DS-A3-0p9p1 Register Name Description 0x400100C0 IOM0IRQ IOM0 Flow Control IRQ Select 0x400100C4 IOM1IRQ IOM1 Flow Control IRQ Select 0x400100C8 IOM2IRQ IOM2 Flow Control IRQ Select 0x400100CC IOM3IRQ IOM3 Flow Control IRQ Select 0x400100D0 IOM4IRQ IOM4 Flow Control IRQ Select 0x400100D4 IOM5IRQ IOM5 Flow Control IRQ Select 0x400100D8 BLEIFIRQ BLEIF Flow Control IRQ Select 0x400100DC GPIOOBS GPIO Observation Mode Samp
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Apollo3 Blue Datasheet 11.7.2 GPIO Registers 11.7.2.1 PADREGA Register Pad Configuration Register A (Pads 0-3) OFFSET: 0x00000000 INSTANCE 0 ADDRESS: 0x40010000 This register controls the pad configuration controls for PAD3 through PAD0. Writes to this register must be unlocked by the PADKEY register.
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Apollo3 Blue Datasheet Table 626: PADREGA Register Bits Bit Name Reset RW 23:22 RSVD 0x0 RO Description RESERVED Pad 2 function select 21:19 PAD2FNCSEL 0x3 RW UART1RX = 0x0 - Configure as the UART1 RX input SLMISO = 0x1 - Configure as the IOSLAVE SPI MISO signal UART0RX = 0x2 - Configure as the UART0 RX input GPIO2 = 0x3 - Configure as GPIO2 RSVD4 = 0x4 - Reserved MSPI6 = 0x5 - CMSPI data connection 6 RSVD6 = 0x6 - Reserved NCE2 = 0x7 - IOM/MSPI nCE group 2 Pad 2 drive strength 18 PAD2STRNG
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Apollo3 Blue Datasheet Table 626: PADREGA Register Bits Bit Name Reset RW Description Pad 0 pullup resistor selection. 7:6 PAD0RSEL 0x0 RW PULL1_5K = 0x0 - Pullup is ~1.
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Apollo3 Blue Datasheet Table 628: PADREGB Register Bits Bit Name Reset RW 31:30 RSVD 0x0 RO Description RESERVED Pad 7 function select 29:27 PAD7FNCSEL 0x3 RW NCE7 = 0x0 - IOM/MSPI nCE group 7 M0MOSI = 0x1 - Configure as the IOMSTR0 SPI MOSI signal CLKOUT = 0x2 - Configure as the CLKOUT signal GPIO7 = 0x3 - Configure as GPIO7 TRIG0 = 0x4 - Configure as the ADC Trigger 0 signal UART0TX = 0x5 - Configure as the UART0 TX output signal RSVD = 0x6 - Reserved CT19 = 0x7 - CTIMER connection 19 Pad 7
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Apollo3 Blue Datasheet Table 628: PADREGB Register Bits Bit Name Reset RW Description Pad 5 pullup resistor selection. 15:14 PAD5RSEL 0x0 RW PULL1_5K = 0x0 - Pullup is ~1.
PAGE 422
Apollo3 Blue Datasheet 11.7.2.3 PADREGC Register Pad Configuration Register C (Pads 8-11) OFFSET: 0x00000008 INSTANCE 0 ADDRESS: 0x40010008 This register controls the pad configuration controls for PAD11 through PAD8. Writes to this register must be unlocked by the PADKEY register.
PAGE 423
Apollo3 Blue Datasheet Table 630: PADREGC Register Bits Bit Name Reset RW Description Pad 10 function select 21:19 PAD10FNCSEL 0x3 RW RSVD0 = 0x0 - Reserved M1MOSI = 0x1 - Configure as the IOMSTR1 SPI MOSI signal NCE10 = 0x2 - IOM/MSPI nCE group 10 GPIO10 = 0x3 - Configure as GPIO10 PDMCLK = 0x4 - PDM serial clock out UA1RTS = 0x5 - Configure as the UART1 RTS output signal RSVD6 = 0x6 - Reserved RSVD7 = 0x7 - REserved Pad 10 drive strength 18 PAD10STRNG 0x0 RW LOW = 0x0 - Low drive strength H
PAGE 424
Apollo3 Blue Datasheet Table 630: PADREGC Register Bits Bit Name Reset RW Description Pad 8 pullup resistor selection. 7:6 PAD8RSEL 0x0 RW PULL1_5K = 0x0 - Pullup is ~1.
PAGE 425
Apollo3 Blue Datasheet Table 632: PADREGD Register Bits Bit Name Reset RW 31:30 RSVD 0x0 RO Description RESERVED Pad 15 function select 29:27 PAD15FNCSEL 0x3 RW ADCD1N = 0x0 - Configure as the analog ADC differential pair 1 N input signal NCE15 = 0x1 - IOM/MSPI nCE group 15 UART1RX = 0x2 - Configure as the UART1 RX signal GPIO15 = 0x3 - Configure as GPIO15 PDMDATA = 0x4 - PDM serial data input SWDIO = 0x6 - Configure as an alternate port for the SWDIO I/O signal SWO = 0x7 - Configure as an SWO
PAGE 426
Apollo3 Blue Datasheet Table 632: PADREGD Register Bits Bit Name Reset RW Description Pad 13 function select 13:11 PAD13FNCSEL 0x3 RW ADCD0PSE8 = 0x0 - Configure as the ADC Differential pair 0 P, or Single Ended input 8 analog input signal.
PAGE 427
Apollo3 Blue Datasheet 11.7.2.5 PADREGE Register Pad Configuration Register E (Pads 16-19) OFFSET: 0x00000010 INSTANCE 0 ADDRESS: 0x40010010 This register controls the pad configuration controls for PAD19 through PAD16. Writes to this register must be unlocked by the PADKEY register.
PAGE 428
Apollo3 Blue Datasheet Table 634: PADREGE Register Bits Bit Name Reset RW Description Pad 18 function select 21:19 PAD18FNCSEL 0x3 RW CMPIN1 = 0x0 - Configure as the analog comparator input 1 signal NCE18 = 0x1 - IOM/MSPI nCE group 18 CT4 = 0x2 - CTIMER connection 4 GPIO18 = 0x3 - Configure as GPIO18 UA0RTS = 0x4 - Configure as UART0 RTS output signal ANATEST2 = 0x5 - Configure as ANATEST2 I/O signal UART1TX = 0x6 - Configure as UART1 TX output signal SCCIO = 0x7 - SCARD data input/output connecti
PAGE 429
Apollo3 Blue Datasheet Table 634: PADREGE Register Bits Bit Name Reset RW Description Pad 16 function select 5:3 PAD16FNCSEL 0x3 RW ADCSE0 = 0x0 - Configure as the analog ADC single ended port 0 input signal NCE16 = 0x1 - IOM/MSPI nCE group 16 TRIG0 = 0x2 - Configure as the ADC Trigger 0 signal GPIO16 = 0x3 - Configure as GPIO16 SCCRST = 0x4 - SCARD reset output CMPIN0 = 0x5 - Configure as comparator input 0 signal UART0TX = 0x6 - Configure as UART0 TX output signal UA1RTS = 0x7 - Configure as UAR
PAGE 430
Apollo3 Blue Datasheet Table 636: PADREGF Register Bits Bit Name Reset RW Description Pad 23 function select 29:27 PAD23FNCSEL 0x3 RW UART0RX = 0x0 - Configure as the UART0 RX signal NCE23 = 0x1 - IOM/MSPI nCE group 23 CT14 = 0x2 - CTIMER connection 14 GPIO23 = 0x3 - Configure as GPIO23 I2SWCLK = 0x4 - I2S word clock input CMPOUT = 0x5 - Configure as voltage comparitor output MSPI3 = 0x6 - MSPI data connection 3 Pad 23 drive strength 26 PAD23STRNG 0x0 RW LOW = 0x0 - Low drive strength HIGH =
PAGE 431
Apollo3 Blue Datasheet Table 636: PADREGF Register Bits Bit Name Reset RW Description Pad 21 function select 13:11 PAD21FNCSEL 0x0 RW SWDIO = 0x0 - Configure as the serial wire debug data signal NCE21 = 0x1 - IOM/MSPI nCE group 21 RSVD = 0x2 - Reserved GPIO21 = 0x3 - Configure as GPIO21 UART0RX = 0x4 - Configure as UART0 RX input signal UART1RX = 0x5 - Configure as UART1 RX input signal I2SBCLK = 0x6 - I2S byte clock input UA1CTS = 0x7 - Configure as UART1 CTS input signal Pad 21 drive strength 1
PAGE 432
Apollo3 Blue Datasheet This register controls the pad configuration controls for PAD27 through PAD24. Writes to this register must be unlocked by the PADKEY register.
PAGE 433
Apollo3 Blue Datasheet Table 638: PADREGG Register Bits Bit Name Reset RW Description Pad 26 function select 21:19 PAD26FNCSEL 0x3 RW NCE26 = 0x1 - IOM/MSPI nCE group 26 CT3 = 0x2 - CTIMER connection 3 GPIO26 = 0x3 - Configure as GPIO26 SCCRST = 0x4 - SCARD reset output MSPI1 = 0x5 - MSPI data connection 1 UART0TX = 0x6 - Configure as UART0 TX output signal UA1CTS = 0x7 - Configure as UART1 CTS input signal Pad 26 drive strength 18 PAD26STRNG 0x0 RW LOW = 0x0 - Low drive strength HIGH = 0x1 -
PAGE 434
Apollo3 Blue Datasheet Table 638: PADREGG Register Bits Bit Name Reset RW Description Pad 24 function select 5:3 PAD24FNCSEL 0x3 RW UART1TX = 0x0 - Configure as UART1 TX output signal NCE24 = 0x1 - IOM/MSPI nCE group 24 MSPI8 = 0x2 - MSPI data connection 8 GPIO24 = 0x3 - Configure as GPIO24 UA0CTS = 0x4 - Configure as UART0 CTS input signal CT21 = 0x5 - CTIMER connection 21 32kHzXT = 0x6 - Configure as the 32kHz crystal output signal SWO = 0x7 - Configure as the serial trace data output signal Pad
PAGE 435
Apollo3 Blue Datasheet Table 640: PADREGH Register Bits Bit Name Reset RW Description Pad 31 function select 29:27 PAD31FNCSEL 0x3 RW ADCSE3 = 0x0 - Configure as the analog input for ADC single ended input 3 NCE31 = 0x1 - IOM/MSPI nCE group 31 CT13 = 0x2 - CTIMER connection 13 GPIO31 = 0x3 - Configure as GPIO31 UART0RX = 0x4 - Configure as the UART0 RX input signal SCCCLK = 0x5 - SCARD serial clock output RSVD = 0x6 - Reserved UA1RTS = 0x7 - Configure as UART1 RTS output signal Pad 31 drive streng
PAGE 436
Apollo3 Blue Datasheet Table 640: PADREGH Register Bits Bit Name Reset RW Description Pad 29 function select 13:11 PAD29FNCSEL 0x3 RW ADCSE1 = 0x0 - Configure as the analog input for ADC single ended input 1 NCE29 = 0x1 - IOM/MSPI nCE group 29 CT9 = 0x2 - CTIMER connection 9 GPIO29 = 0x3 - Configure as GPIO29 UA0CTS = 0x4 - Configure as the UART0 CTS input signal UA1CTS = 0x5 - Configure as the UART1 CTS input signal UART0RX = 0x6 - Configure as the UART0 RX input signal PDM_DATA = 0x7 - Configure
PAGE 437
Apollo3 Blue Datasheet This register controls the pad configuration controls for PAD35 through PAD32. Writes to this register must be unlocked by the PADKEY register.
PAGE 438
Apollo3 Blue Datasheet Table 642: PADREGI Register Bits Bit Name Reset RW Description Pad 34 drive strength 18 PAD34STRNG 0x0 RW LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength Pad 34 input enable 17 PAD34INPEN 0x0 RW DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled Pad 34 pullup enable 16 PAD34PULL 0x0 RW 15:14 RSVD 0x0 RO DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled RESERVED Pad 33 function select 13:11 PAD33FNCSEL 0x3 RW ADCSE5 = 0x0 - Conf
PAGE 439
Apollo3 Blue Datasheet Table 642: PADREGI Register Bits Bit Name Reset RW Description Pad 32 input enable 1 PAD32INPEN 0x0 RW DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled Pad 32 pullup enable 0 PAD32PULL 0x0 RW DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled 11.7.2.10PADREGJ Register Pad Configuration Register J (Pads 36-39) OFFSET: 0x00000024 INSTANCE 0 ADDRESS: 0x40010024 This register controls the pad configuration controls for PAD39 through PAD36.
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Apollo3 Blue Datasheet Table 644: PADREGJ Register Bits Bit Name Reset RW Description Pad 39 drive strength 26 PAD39STRNG 0x0 RW LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength Pad 39 input enable 25 PAD39INPEN 0x0 RW DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled Pad 39 pullup enable 24 PAD39PULL 0x0 RW 23:22 RSVD 0x0 RO DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled RESERVED Pad 38 function select 21:19 PAD38FNCSEL 0x3 RW TRIG3 = 0x0 - Confi
PAGE 441
Apollo3 Blue Datasheet Table 644: PADREGJ Register Bits Bit Name Reset RW Description Pad 37 drive strength 10 PAD37STRNG 0x0 RW LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength Pad 37 input enable 9 PAD37INPEN 0x0 RW DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled Pad 37 pullup enable 8 PAD37PULL 0x0 RW 7 RSVD 0x0 RO DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled RESERVED Pad 36 VDD power switch enable 6 PAD36PWRUP 0x0 RW DIS = 0x0 - Power swit
PAGE 442
Apollo3 Blue Datasheet 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 PAD40PULL 1 2 PAD40INPEN 1 3 PAD40STRNG 1 4 PAD40FNCSEL 1 5 PAD40RSEL 1 6 PAD41PULL 1 7 PAD41INPEN 1 8 PAD41STRNG 1 9 PAD41FNCSEL 2 0 RSVD 2 1 PAD42PULL 2 2 PAD41PWRDN 2 3 PAD42INPEN 2 4 PAD42STRNG 2 5 PAD42FNCSEL 2 6 PAD42RSEL 2 7 PAD43PULL 2 8 PAD43INPEN 2 9 PAD43FNCSEL 3 0 PAD43RSEL 3 1 PAD43STRNG Table 645: PADREGK Register Table 646: PADREGK Register Bits Bit Name Reset RW De
PAGE 443
Apollo3 Blue Datasheet Table 646: PADREGK Register Bits Bit Name Reset RW Description Pad 42 function select 21:19 PAD42FNCSEL 0x3 RW UART1TX = 0x0 - Configure as the UART1 TX output signal NCE42 = 0x1 - IOM/MSPI nCE group 42 CT16 = 0x2 - CTIMER connection 16 GPIO42 = 0x3 - Configure as GPIO42 M3SCL = 0x4 - Configure as the IOMSTR3 I2C SCL clock I/O signal M3SCK = 0x5 - Configure as the IOMSTR3 SPI SCK output RSVD6 = 0x6 - Reserved RSVD7 = 0x7 - Reserved Pad 42 drive strength 18 PAD42STRNG 0x0
PAGE 444
Apollo3 Blue Datasheet Table 646: PADREGK Register Bits Bit Name Reset RW Description Pad 40 pullup resistor selection. 7:6 PAD40RSEL 0x0 RW PULL1_5K = 0x0 - Pullup is ~1.
PAGE 445
Apollo3 Blue Datasheet Table 648: PADREGL Register Bits Bit Name Reset RW 31:30 RSVD 0x0 RO Description RESERVED Pad 47 function select 29:27 PAD47FNCSEL 0x3 RW 32kHzXT = 0x0 - Configure as the 32kHz output clock from the crystal NCE47 = 0x1 - IOM/MSPI nCE group 47 CT26 = 0x2 - CTIMER connection 26 GPIO47 = 0x3 - Configure as GPIO47 RSVD4 = 0x4 - Reserved M5MOSI = 0x5 - Configure as the IOMSTR5 SPI MOSI output signal UART1RX = 0x6 - Configure as the UART1 RX input signal RSVD7 = 0x7 - Reserved
PAGE 446
Apollo3 Blue Datasheet Table 648: PADREGL Register Bits Bit Name Reset RW Description Pad 45 function select 13:11 PAD45FNCSEL 0x3 RW UA1CTS = 0x0 - Configure as the UART1 CTS input signal NCE45 = 0x1 - IOM/MSPI nCE group 45 CT22 = 0x2 - CTIMER connection 22 GPIO45 = 0x3 - Configure as GPIO45 I2SDAT = 0x4 - I2S serial data output PDMDATA = 0x5 - PDM serial data input UART0RX = 0x6 - Configure as the SPI channel 5 nCE signal from IOMSTR5 SWO = 0x7 - Configure as the serial wire debug SWO signal Pad
PAGE 447
Apollo3 Blue Datasheet This register controls the pad configuration controls for PAD49 through PAD48. Writes to this register must be unlocked by the PADKEY register.
PAGE 448
Apollo3 Blue Datasheet Table 650: PADREGM Register Bits Bit Name Reset RW Description Pad 48 pullup resistor selection. 7:6 PAD48RSEL 0x0 PULL1_5K = 0x0 - Pullup is ~1.
PAGE 449
Apollo3 Blue Datasheet Table 652: CFGA Register Bits Bit Name Reset RW Description GPIO7 interrupt direction, nCE polarity.
PAGE 450
Apollo3 Blue Datasheet Table 652: CFGA Register Bits Bit Name Reset RW Description GPIO5 output configuration. 22:21 GPIO5OUTCFG 0x0 RW DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state GPIO5 input enable.
PAGE 451
Apollo3 Blue Datasheet Table 652: CFGA Register Bits Bit Name Reset RW Description GPIO3 output configuration.
PAGE 452
Apollo3 Blue Datasheet Table 652: CFGA Register Bits Bit Name Reset RW Description GPIO1 output configuration.
PAGE 453
Apollo3 Blue Datasheet 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 GPIO8INCFG 0 9 GPIO8OUTCFG 1 0 GPIO8INTD 1 1 GPIO9INCFG 1 2 GPIO9OUTCFG 1 3 GPIO9INTD 1 4 GPIO10INCFG 1 5 GPIO10OUTCFG 1 6 GPIO10INTD 1 7 GPIO11INCFG 1 8 GPIO11OUTCFG 1 9 GPIO11INTD 2 0 GPIO12INCFG 2 1 GPIO12OUTCFG 2 2 GPIO12INTD 2 3 GPIO13INCFG 2 4 GPIO13OUTCFG 2 5 GPIO13INTD 2 6 GPIO14INCFG 2 7 GPIO14OUTCFG 2 8 GPIO14INTD 2 9 GPIO15OUTCFG 3 0 GPIO15INTD 3 1 GPIO15INCFG Table 653: CFGB Registe
PAGE 454
Apollo3 Blue Datasheet Table 654: CFGB Register Bits Bit Name Reset RW Description GPIO14 output configuration.
PAGE 455
Apollo3 Blue Datasheet Table 654: CFGB Register Bits Bit Name Reset RW Description GPIO12 output configuration.
PAGE 456
Apollo3 Blue Datasheet Table 654: CFGB Register Bits Bit Name Reset RW Description GPIO10 output configuration.
PAGE 457
Apollo3 Blue Datasheet Table 654: CFGB Register Bits Bit Name Reset RW Description GPIO8 output configuration.
PAGE 458
Apollo3 Blue Datasheet Table 656: CFGC Register Bits Bit Name Reset RW Description GPIO23 interrupt direction.
PAGE 459
Apollo3 Blue Datasheet Table 656: CFGC Register Bits Bit Name Reset RW Description GPIO21 interrupt direction.
PAGE 460
Apollo3 Blue Datasheet Table 656: CFGC Register Bits Bit Name Reset RW Description GPIO19 interrupt direction.
PAGE 461
Apollo3 Blue Datasheet Table 656: CFGC Register Bits Bit Name Reset RW Description GPIO17 interrupt direction.
PAGE 462
Apollo3 Blue Datasheet 11.7.2.17CFGD Register GPIO Configuration Register D (Pads 24-31) OFFSET: 0x0000004C INSTANCE 0 ADDRESS: 0x4001004C GPIO configuration controls for GPIO[31:24]. Writes to this register must be unlocked by the PADKEY register.
PAGE 463
Apollo3 Blue Datasheet Table 658: CFGD Register Bits Bit Name Reset RW Description GPIO30 interrupt direction.
PAGE 464
Apollo3 Blue Datasheet Table 658: CFGD Register Bits Bit Name Reset RW Description GPIO28 interrupt direction.
PAGE 465
Apollo3 Blue Datasheet Table 658: CFGD Register Bits Bit Name Reset RW Description GPIO26 interrupt direction.
PAGE 466
Apollo3 Blue Datasheet Table 658: CFGD Register Bits Bit Name Reset RW Description GPIO24 interrupt direction.
PAGE 467
Apollo3 Blue Datasheet Table 660: CFGE Register Bits Bit Name Reset RW Description GPIO39 interrupt direction. 31 GPIO39INTD 0x0 RW INTDIS = 0x0 - INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - INCFG = 0 - Interrupt on high to low GPIO transition GPIO39 output configuration.
PAGE 468
Apollo3 Blue Datasheet Table 660: CFGE Register Bits Bit Name Reset RW Description GPIO37 interrupt direction.
PAGE 469
Apollo3 Blue Datasheet Table 660: CFGE Register Bits Bit Name Reset RW Description GPIO35 interrupt direction.
PAGE 470
Apollo3 Blue Datasheet Table 660: CFGE Register Bits Bit Name Reset RW Description GPIO33 interrupt direction.
PAGE 471
Apollo3 Blue Datasheet 11.7.2.19CFGF Register GPIO Configuration Register F (Pads 40 -47) OFFSET: 0x00000054 INSTANCE 0 ADDRESS: 0x40010054 GPIO configuration controls for GPIO[47:40]. Writes to this register must be unlocked by the PADKEY register.
PAGE 472
Apollo3 Blue Datasheet Table 662: CFGF Register Bits Bit Name Reset RW Description GPIO46 interrupt direction.
PAGE 473
Apollo3 Blue Datasheet Table 662: CFGF Register Bits Bit Name Reset RW Description GPIO44 interrupt direction.
PAGE 474
Apollo3 Blue Datasheet Table 662: CFGF Register Bits Bit Name Reset RW Description GPIO42 interrupt direction.
PAGE 475
Apollo3 Blue Datasheet Table 662: CFGF Register Bits Bit Name Reset RW Description GPIO40 interrupt direction. 3 GPIO40INTD 0x0 RW INTDIS = 0x0 - INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - INCFG = 0 - Interrupt on high to low GPIO transition GPIO40 output configuration.
PAGE 476
Apollo3 Blue Datasheet Table 664: CFGG Register Bits Bit Name Reset RW Description GPIO49 interrupt direction.
PAGE 477
Apollo3 Blue Datasheet 11.7.2.
PAGE 478
Apollo3 Blue Datasheet INSTANCE 0 ADDRESS: 0x40010084 GPIO Input Register B Table 669: RDB Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 RSVD 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RDB Table 670: RDB Register Bits Bit Name Reset RW 31:18 RSVD 0x0 RO 17:0 RDB 0x0 RO Description RESERVED GPIO49-32 read data. 11.7.2.
PAGE 479
Apollo3 Blue Datasheet Table 673: WTB Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 RSVD 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 WTB Table 674: WTB Register Bits Bit Name Reset RW 31:18 RSVD 0x0 RO 17:0 WTB 0x0 RW Description RESERVED GPIO49-32 write data. 11.7.2.
PAGE 480
Apollo3 Blue Datasheet Table 677: WTSB Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 RSVD 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 WTSB Table 678: WTSB Register Bits Bit Name Reset RW 31:18 RSVD 0x0 RO 17:0 WTSB 0x0 WO Description RESERVED Set the GPIO49-32 write data. 11.7.2.
PAGE 481
Apollo3 Blue Datasheet Table 681: WTCB Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 RSVD 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 WTCB Table 682: WTCB Register Bits Bit Name Reset RW 31:18 RSVD 0x0 RO 17:0 WTCB 0x0 WO Description RESERVED Clear the GPIO49-32 write data. 11.7.2.
PAGE 482
Apollo3 Blue Datasheet Table 685: ENB Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 RSVD 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ENB Table 686: ENB Register Bits Bit Name Reset RW 31:18 RSVD 0x0 RO 17:0 ENB 0x0 RW Description RESERVED GPIO49-32 output enables 11.7.2.
PAGE 483
Apollo3 Blue Datasheet Table 689: ENSB Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 RSVD 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ENSB Table 690: ENSB Register Bits Bit Name Reset RW 31:18 RSVD 0x0 RO 17:0 ENSB 0x0 RW Description RESERVED Set the GPIO49-32 output enables 11.7.2.
PAGE 484
Apollo3 Blue Datasheet 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 RSVD 0 9 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 STPOL0 3 1 RSVD Table 693: ENCB Register 0 8 ENCB Table 694: ENCB Register Bits Bit Name Reset RW 31:18 RSVD 0x0 RO 17:0 ENCB 0x0 RW Description RESERVED Clear the GPIO49-32 output enables 11.7.2.
PAGE 485
Apollo3 Blue Datasheet Table 696: STMRCAP Register Bits Bit Name Reset RW Description STIMER Capture 2 Polarity. 22 STPOL2 0x0 RW 21:16 STSEL2 0x3f RW 15 RSVD 0x0 RO CAPLH = 0x0 - Capture on low to high GPIO transition CAPHL = 0x1 - Capture on high to low GPIO transition STIMER Capture 2 Select. RESERVED STIMER Capture 1 Polarity.
PAGE 486
Apollo3 Blue Datasheet 11.7.2.38IOM1IRQ Register IOM1 Flow Control IRQ Select OFFSET: 0x000000C4 INSTANCE 0 ADDRESS: 0x400100C4 IOMSTR1 IRQ select for flow control.
PAGE 487
Apollo3 Blue Datasheet 11.7.2.40IOM3IRQ Register IOM3 Flow Control IRQ Select OFFSET: 0x000000CC INSTANCE 0 ADDRESS: 0x400100CC IOMSTR3 IRQ select for flow control.
PAGE 488
Apollo3 Blue Datasheet 11.7.2.42IOM5IRQ Register IOM5 Flow Control IRQ Select OFFSET: 0x000000D4 INSTANCE 0 ADDRESS: 0x400100D4 IOMSTR5 IRQ select for flow control.
PAGE 489
Apollo3 Blue Datasheet 11.7.2.
PAGE 490
Apollo3 Blue Datasheet Table 714: ALTPADCFGA Register Bits Bit Name Reset RW 28 PAD3_SR 0x0 RW Description Pad 3 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad 27:25 RSVD 0x0 RO 24 PAD3_DS1 0x0 RW 23:21 RSVD 0x0 RO 20 PAD2_SR 0x0 RW RESERVED Pad 3 high order drive strength selection. Used in conjunction with PAD3STRNG field to set the pad drive strength. RESERVED Pad 2 slew rate selection.
PAGE 491
Apollo3 Blue Datasheet Table 715: ALTPADCFGB Register 2 3 2 2 2 1 RSVD 2 0 1 9 1 8 1 7 RSVD 1 6 1 5 1 4 RSVD 1 3 1 2 1 1 1 0 RSVD 0 9 0 8 0 7 0 6 0 5 RSVD 0 4 0 3 0 2 RSVD 0 1 0 0 PAD4_DS1 2 4 PAD4_SR RSVD 2 5 PAD5_DS1 2 6 PAD5_SR 2 7 PAD6_DS1 RSVD 2 8 PAD6_SR 2 9 PAD7_DS1 3 0 PAD7_SR 3 1 Table 716: ALTPADCFGB Register Bits Bit Name Reset RW 31:29 RSVD 0x0 RO 28 PAD7_SR 0x0 RW Description RESERVED Pad 7 slew rate selection.
PAGE 492
Apollo3 Blue Datasheet Table 716: ALTPADCFGB Register Bits Bit Name Reset RW 3:1 RSVD 0x0 RO 0 PAD4_DS1 0x0 RW Description RESERVED Pad 4 high order drive strength selection. Used in conjunction with PAD4STRNG field to set the pad drive strength. 11.7.2.
PAGE 493
Apollo3 Blue Datasheet Table 718: ALTPADCFGC Register Bits Bit Name Reset RW 15:13 RSVD 0x0 RO 12 PAD9_SR 0x0 RW Description RESERVED Pad 9 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad 11:9 RSVD 0x0 RO 8 PAD9_DS1 0x0 RW 7:5 RSVD 0x0 RO 4 PAD8_SR 0x0 RW RESERVED Pad 9 high order drive strength selection. Used in conjunction with PAD9STRNG field to set the pad drive strength. RESERVED Pad 8 slew rate selection.
PAGE 494
Apollo3 Blue Datasheet Table 720: ALTPADCFGD Register Bits Bit Name Reset RW 27:25 RSVD 0x0 RO 24 PAD15_DS1 0x0 RW 23:21 RSVD 0x0 RO 20 PAD14_SR 0x0 RW Description RESERVED Pad 15 high order drive strength selection. Used in conjunction with PAD15STRNG field to set the pad drive strength. RESERVED Pad 14 slew rate selection.
PAGE 495
Apollo3 Blue Datasheet Table 721: ALTPADCFGE Register 2 3 2 2 2 1 RSVD 2 0 1 9 1 8 1 7 RSVD 1 6 1 5 1 4 RSVD 1 3 1 2 1 1 1 0 RSVD 0 9 0 8 0 7 0 6 0 5 RSVD 0 4 0 3 0 2 RSVD 0 1 0 0 PAD16_DS1 RSVD 2 4 PAD16_SR 2 5 PAD17_DS1 2 6 PAD17_SR 2 7 PAD18_DS1 RSVD 2 8 PAD18_SR 2 9 PAD19_DS1 3 0 PAD19_SR 3 1 Table 722: ALTPADCFGE Register Bits Bit Name Reset RW 31:29 RSVD 0x0 RO 28 PAD19_SR 0x0 RW Description RESERVED Pad 19 slew rate selection.
PAGE 496
Apollo3 Blue Datasheet Table 722: ALTPADCFGE Register Bits Bit Name Reset RW 3:1 RSVD 0x0 RO 0 PAD16_DS1 0x0 RW Description RESERVED Pad 16 high order drive strength selection. Used in conjunction with PAD16STRNG field to set the pad drive strength. 11.7.2.
PAGE 497
Apollo3 Blue Datasheet Table 724: ALTPADCFGF Register Bits Bit Name Reset RW 15:13 RSVD 0x0 RO 12 PAD21_SR 0x0 RW Description RESERVED Pad 21 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad 11:9 RSVD 0x0 RO 8 PAD21_DS1 0x0 RW 7:5 RSVD 0x0 RO 4 PAD20_SR 0x0 RW RESERVED Pad 21 high order drive strength selection. Used in conjunction with PAD21STRNG field to set the pad drive strength. RESERVED Pad 20 slew rate selection.
PAGE 498
Apollo3 Blue Datasheet Table 726: ALTPADCFGG Register Bits Bit Name Reset RW 27:25 RSVD 0x0 RO 24 PAD27_DS1 0x0 RW 23:21 RSVD 0x0 RO 20 PAD26_SR 0x0 RW Description RESERVED Pad 27 high order drive strength selection. Used in conjunction with PAD27STRNG field to set the pad drive strength. RESERVED Pad 26 slew rate selection.
PAGE 499
Apollo3 Blue Datasheet Table 727: ALTPADCFGH Register 2 3 2 2 2 1 RSVD 2 0 1 9 1 8 1 7 RSVD 1 6 1 5 1 4 RSVD 1 3 1 2 1 1 1 0 RSVD 0 9 0 8 0 7 0 6 0 5 RSVD 0 4 0 3 0 2 RSVD 0 1 0 0 PAD28_DS1 RSVD 2 4 PAD28_SR 2 5 PAD29_DS1 2 6 PAD29_SR 2 7 PAD30_DS1 RSVD 2 8 PAD30_SR 2 9 PAD31_DS1 3 0 PAD31_SR 3 1 Table 728: ALTPADCFGH Register Bits Bit Name Reset RW 31:29 RSVD 0x0 RO 28 PAD31_SR 0x0 RW Description RESERVED Pad 31 slew rate selection.
PAGE 500
Apollo3 Blue Datasheet Table 728: ALTPADCFGH Register Bits Bit Name Reset RW 3:1 RSVD 0x0 RO 0 PAD28_DS1 0x0 RW Description RESERVED Pad 28 high order drive strength selection. Used in conjunction with PAD28STRNG field to set the pad drive strength. 11.7.2.
PAGE 501
Apollo3 Blue Datasheet Table 730: ALTPADCFGI Register Bits Bit Name Reset RW 15:13 RSVD 0x0 RO 12 PAD33_SR 0x0 RW Description RESERVED Pad 33 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad 11:9 RSVD 0x0 RO 8 PAD33_DS1 0x0 RW 7:5 RSVD 0x0 RO 4 PAD32_SR 0x0 RW RESERVED Pad 33 high order drive strength selection. Used in conjunction with PAD33STRNG field to set the pad drive strength. RESERVED Pad 32 slew rate selection.
PAGE 502
Apollo3 Blue Datasheet Table 732: ALTPADCFGJ Register Bits Bit Name Reset RW 27:25 RSVD 0x0 RO 24 PAD39_DS1 0x0 RW 23:21 RSVD 0x0 RO 20 PAD38_SR 0x0 RW Description RESERVED Pad 39 high order drive strength selection. Used in conjunction with PAD39STRNG field to set the pad drive strength. RESERVED Pad 38 slew rate selection.
PAGE 503
Apollo3 Blue Datasheet Table 733: ALTPADCFGK Register 2 3 2 2 2 1 RSVD 2 0 1 9 1 8 1 7 RSVD 1 6 1 5 1 4 RSVD 1 3 1 2 1 1 1 0 RSVD 0 9 0 8 0 7 0 6 0 5 RSVD 0 4 0 3 0 2 RSVD 0 1 0 0 PAD40_DS1 RSVD 2 4 PAD40_SR 2 5 PAD41_DS1 2 6 PAD41_SR 2 7 PAD42_DS1 RSVD 2 8 PAD42_SR 2 9 PAD43_DS1 3 0 PAD43_SR 3 1 Table 734: ALTPADCFGK Register Bits Bit Name Reset RW 31:29 RSVD 0x0 RO 28 PAD43_SR 0x0 RW Description RESERVED Pad 43 slew rate selection.
PAGE 504
Apollo3 Blue Datasheet Table 734: ALTPADCFGK Register Bits Bit Name Reset RW 3:1 RSVD 0x0 RO 0 PAD40_DS1 0x0 RW Description RESERVED Pad 40 high order drive strength selection. Used in conjunction with PAD40STRNG field to set the pad drive strength. 11.7.2.
PAGE 505
Apollo3 Blue Datasheet Table 736: ALTPADCFGL Register Bits Bit Name Reset RW 15:13 RSVD 0x0 RO 12 PAD45_SR 0x0 RW Description RESERVED Pad 45 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad 11:9 RSVD 0x0 RO 8 PAD45_DS1 0x0 RW 7:5 RSVD 0x0 RO 4 PAD44_SR 0x0 RW RESERVED Pad 45 high order drive strength selection. Used in conjunction with PAD45STRNG field to set the pad drive strength. RESERVED Pad 44 slew rate selection.
PAGE 506
Apollo3 Blue Datasheet Table 738: ALTPADCFGM Register Bits Bit Name Reset RW 11:9 RSVD 0x0 RO 8 PAD49_DS1 0x0 RW 7:5 RSVD 0x0 RO 4 PAD48_SR 0x0 RW Description RESERVED Pad 49 high order drive strength selection. Used in conjunction with PAD49STRNG field to set the pad drive strength. RESERVED Pad 48 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad 3:1 RSVD 0x0 RO 0 PAD48_DS1 0x0 RW RESERVED Pad 48 high order drive strength selection.
PAGE 507
Apollo3 Blue Datasheet EN22 EN21 EN20 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 EN0 EN23 1 2 EN1 EN24 1 3 EN2 EN25 1 4 EN3 EN26 1 5 EN4 EN27 1 6 EN5 EN28 1 7 EN6 EN29 1 8 EN7 EN30 1 9 EN8 2 0 EN9 2 1 EN11 2 2 EN10 2 3 EN12 2 4 EN13 2 5 EN14 2 6 EN15 2 7 EN16 2 8 EN17 2 9 EN18 3 0 EN19 3 1 EN31 Table 741: CTENCFG Register Table 742: CTENCFG Register Bits Bit Name Reset RW Description CT31 Enable 31 EN31 0x1 RW DIS = 0x1 - Disable
PAGE 508
Apollo3 Blue Datasheet Table 742: CTENCFG Register Bits Bit Name Reset RW Description CT21 Enable 21 EN21 0x1 RW DIS = 0x1 - Disable CT21 for output EN = 0x0 - Enable CT21 for output CT20 Enable 20 EN20 0x1 RW DIS = 0x1 - Disable CT20 for output EN = 0x0 - Enable CT20 for output CT19 Enable 19 EN19 0x1 RW DIS = 0x1 - Disable CT19 for output EN = 0x0 - Enable CT19 for output CT18 Enable 18 EN18 0x1 RW DIS = 0x1 - Disable CT18 for output EN = 0x0 - Enable CT18 for output CT17 Enable
PAGE 509
Apollo3 Blue Datasheet Table 742: CTENCFG Register Bits Bit Name Reset RW Description CT8 Enable 8 EN8 0x1 RW DIS = 0x1 - Disable CT8 for output EN = 0x0 - Enable CT8 for output CT7 Enable 7 EN7 0x1 RW DIS = 0x1 - Disable CT7 for output EN = 0x0 - Enable CT7 for output CT6 Enable 6 EN6 0x1 RW DIS = 0x1 - Disable CT6 for output EN = 0x0 - Enable CT6 for output CT5 Enable 5 EN5 0x1 RW DIS = 0x1 - Disable CT5 for output EN = 0x0 - Enable CT5 for output CT4 Enable 4 EN4 0x1 RW DIS
PAGE 510
Apollo3 Blue Datasheet 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 GPIO0 GPIO21 1 1 GPIO1 GPIO22 1 2 GPIO2 GPIO23 1 3 GPIO3 GPIO24 1 4 GPIO4 GPIO25 1 5 GPIO5 GPIO26 1 6 GPIO6 GPIO27 1 7 GPIO7 GPIO28 1 8 GPIO8 GPIO29 1 9 GPIO9 GPIO30 2 0 GPIO11 2 1 GPIO10 2 2 GPIO12 2 3 GPIO13 2 4 GPIO14 2 5 GPIO15 2 6 GPIO16 2 7 GPIO17 2 8 GPIO18 2 9 GPIO19 3 0 GPIO20 3 1 GPIO31 Table 743: INT0EN Register Table 744: INT0EN Register Bits Bit Name Reset RW 31
PAGE 511
Apollo3 Blue Datasheet Table 744: INT0EN Register Bits Bit Name Reset RW 13 GPIO13 0x0 RW 12 GPIO12 0x0 RW 11 GPIO11 0x0 RW 10 GPIO10 0x0 RW 9 GPIO9 0x0 RW 8 GPIO8 0x0 RW 7 GPIO7 0x0 RW 6 GPIO6 0x0 RW 5 GPIO5 0x0 RW 4 GPIO4 0x0 RW 3 GPIO3 0x0 RW 2 GPIO2 0x0 RW 1 GPIO1 0x0 RW 0 GPIO0 0x0 RW Description GPIO13 interrupt. GPIO12 interrupt. GPIO11 interrupt. GPIO10 interrupt. GPIO9 interrupt. GPIO8 interrupt. GPIO7 interrupt. GPIO6 interrupt.
PAGE 512
Apollo3 Blue Datasheet Table 746: INT0STAT Register Bits Bit Name Reset RW 31 GPIO31 0x0 RW 30 GPIO30 0x0 RW 29 GPIO29 0x0 RW 28 GPIO28 0x0 RW 27 GPIO27 0x0 RW 26 GPIO26 0x0 RW 25 GPIO25 0x0 RW 24 GPIO24 0x0 RW 23 GPIO23 0x0 RW 22 GPIO22 0x0 RW 21 GPIO21 0x0 RW 20 GPIO20 0x0 RW 19 GPIO19 0x0 RW 18 GPIO18 0x0 RW 17 GPIO17 0x0 RW 16 GPIO16 0x0 RW 15 GPIO15 0x0 RW 14 GPIO14 0x0 RW 13 GPIO13 0x0 RW 12 GPIO12 0x0 RW 11 GPIO11
PAGE 513
Apollo3 Blue Datasheet Table 746: INT0STAT Register Bits Bit Name Reset RW 9 GPIO9 0x0 RW 8 GPIO8 0x0 RW 7 GPIO7 0x0 RW 6 GPIO6 0x0 RW 5 GPIO5 0x0 RW 4 GPIO4 0x0 RW 3 GPIO3 0x0 RW 2 GPIO2 0x0 RW 1 GPIO1 0x0 RW 0 GPIO0 0x0 RW Description GPIO9 interrupt. GPIO8 interrupt. GPIO7 interrupt. GPIO6 interrupt. GPIO5 interrupt. GPIO4 interrupt. GPIO3 interrupt. GPIO2 interrupt. GPIO1 interrupt. GPIO0 interrupt. 11.7.2.
PAGE 514
Apollo3 Blue Datasheet Table 748: INT0CLR Register Bits Bit Name Reset RW 29 GPIO29 0x0 RW 28 GPIO28 0x0 RW 27 GPIO27 0x0 RW 26 GPIO26 0x0 RW 25 GPIO25 0x0 RW 24 GPIO24 0x0 RW 23 GPIO23 0x0 RW 22 GPIO22 0x0 RW 21 GPIO21 0x0 RW 20 GPIO20 0x0 RW 19 GPIO19 0x0 RW 18 GPIO18 0x0 RW 17 GPIO17 0x0 RW 16 GPIO16 0x0 RW 15 GPIO15 0x0 RW 14 GPIO14 0x0 RW 13 GPIO13 0x0 RW 12 GPIO12 0x0 RW 11 GPIO11 0x0 RW 10 GPIO10 0x0 RW 9 GPIO9 0x0
PAGE 515
Apollo3 Blue Datasheet Table 748: INT0CLR Register Bits Bit Name Reset RW 6 GPIO6 0x0 RW 5 GPIO5 0x0 RW 4 GPIO4 0x0 RW 3 GPIO3 0x0 RW 2 GPIO2 0x0 RW 1 GPIO1 0x0 RW 0 GPIO0 0x0 RW Description GPIO6 interrupt. GPIO5 interrupt. GPIO4 interrupt. GPIO3 interrupt. GPIO2 interrupt. GPIO1 interrupt. GPIO0 interrupt. 11.7.2.
PAGE 516
Apollo3 Blue Datasheet Table 750: INT0SET Register Bits Bit Name Reset RW 26 GPIO26 0x0 RW 25 GPIO25 0x0 RW 24 GPIO24 0x0 RW 23 GPIO23 0x0 RW 22 GPIO22 0x0 RW 21 GPIO21 0x0 RW 20 GPIO20 0x0 RW 19 GPIO19 0x0 RW 18 GPIO18 0x0 RW 17 GPIO17 0x0 RW 16 GPIO16 0x0 RW 15 GPIO15 0x0 RW 14 GPIO14 0x0 RW 13 GPIO13 0x0 RW 12 GPIO12 0x0 RW 11 GPIO11 0x0 RW 10 GPIO10 0x0 RW 9 GPIO9 0x0 RW 8 GPIO8 0x0 RW 7 GPIO7 0x0 RW 6 GPIO6 0x0 RW
PAGE 517
Apollo3 Blue Datasheet Table 750: INT0SET Register Bits Bit Name Reset RW 3 GPIO3 0x0 RW 2 GPIO2 0x0 RW 1 GPIO1 0x0 RW 0 GPIO0 0x0 RW Description GPIO3 interrupt. GPIO2 interrupt. GPIO1 interrupt. GPIO0 interrupt. 11.7.2.64INT1EN Register GPIO Interrupt Registers 49-32: Enable OFFSET: 0x00000210 INSTANCE 0 ADDRESS: 0x40010210 Set bits in this register to allow this module to generate the corresponding interrupt.
PAGE 518
Apollo3 Blue Datasheet Table 752: INT1EN Register Bits Bit Name Reset RW 10 GPIO42 0x0 RW 9 GPIO41 0x0 RW 8 GPIO40 0x0 RW 7 GPIO39 0x0 RW 6 GPIO38 0x0 RW 5 GPIO37 0x0 RW 4 GPIO36 0x0 RW 3 GPIO35 0x0 RW 2 GPIO34 0x0 RW 1 GPIO33 0x0 RW 0 GPIO32 0x0 RW Description GPIO42 interrupt. GPIO41 interrupt. GPIO40 interrupt. GPIO39 interrupt. GPIO38 interrupt. GPIO37 interrupt. GPIO36 interrupt. GPIO35 interrupt. GPIO34 interrupt. GPIO33 interrupt. GPIO32 interrupt.
PAGE 519
Apollo3 Blue Datasheet Table 754: INT1STAT Register Bits Bit Name Reset RW 17 GPIO49 0x0 RW 16 GPIO48 0x0 RW 15 GPIO47 0x0 RW 14 GPIO46 0x0 RW 13 GPIO45 0x0 RW 12 GPIO44 0x0 RW 11 GPIO43 0x0 RW 10 GPIO42 0x0 RW 9 GPIO41 0x0 RW 8 GPIO40 0x0 RW 7 GPIO39 0x0 RW 6 GPIO38 0x0 RW 5 GPIO37 0x0 RW 4 GPIO36 0x0 RW 3 GPIO35 0x0 RW 2 GPIO34 0x0 RW 1 GPIO33 0x0 RW 0 GPIO32 0x0 RW Description GPIO49 interrupt. GPIO48 interrupt.
PAGE 520
Apollo3 Blue Datasheet 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 GPIO32 1 5 GPIO33 1 6 GPIO34 1 7 GPIO35 RSVD 1 8 GPIO36 1 9 GPIO37 2 0 GPIO38 2 1 GPIO39 2 2 GPIO40 2 3 GPIO41 2 4 GPIO42 2 5 GPIO43 2 6 GPIO44 2 7 GPIO45 2 8 GPIO46 2 9 GPIO47 3 0 GPIO48 3 1 GPIO49 Table 755: INT1CLR Register Table 756: INT1CLR Register Bits Bit Name Reset RW 31:18 RSVD 0x0 RO 17 GPIO49 0x0 RW 16 GPIO48 0x0 RW 15 GPIO47 0x0 RW 14 GPIO46
PAGE 521
Apollo3 Blue Datasheet Table 756: INT1CLR Register Bits Bit Name Reset RW 0 GPIO32 0x0 RW Description GPIO32 interrupt. 11.7.2.67INT1SET Register GPIO Interrupt Registers 49-32: Set OFFSET: 0x0000021C INSTANCE 0 ADDRESS: 0x4001021C Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
PAGE 522
Apollo3 Blue Datasheet Table 758: INT1SET Register Bits Bit Name Reset RW 7 GPIO39 0x0 RW 6 GPIO38 0x0 RW 5 GPIO37 0x0 RW 4 GPIO36 0x0 RW 3 GPIO35 0x0 RW 2 GPIO34 0x0 RW 1 GPIO33 0x0 RW 0 GPIO32 0x0 RW DS-A3-0p9p1 Description GPIO39 interrupt. GPIO38 interrupt. GPIO37 interrupt. GPIO36 interrupt. GPIO35 interrupt. GPIO34 interrupt. GPIO33 interrupt. GPIO32 interrupt. Page 522 of 909 2019 Ambiq Micro, Inc. All rights reserved.
PAGE 523
Apollo3 Blue Datasheet 12. Clock Generator and Real Time Clock Module Calibration Registers Autocal Logic XT Osc XT Chain LFRC Osc LFRC Chain Module Clocks HFRC Osc HFRC Chain Core, Flash CLKOUT 100 Hz CLKOUT RTC Figure 63. Block diagram for the Clock Generator and Real Time Clock Module 12.1 Clock Generator 12.1.1 Functional Overview A high-level view of the Clock Generator Module, which supplies all clocks required by the Apollo3 Blue MCU, is shown in Figure 63.
PAGE 524
Apollo3 Blue Datasheet software intervention, so that software does not need to manage any enabling or disabling of the oscillators. As an example, an I2C/SPI Master requires the HFRC in order to generate the serial interface clock. If a transfer is initiated and the processor is put into Deep Sleep mode, the HFRC will remain active until the I/O transfer is completed. At that point the HFRC will be powered down without requiring any software intervention.
PAGE 525
Apollo3 Blue Datasheet 12.1.2.1 LFRC Oscillator Digital Calibration The LFRC Oscillator includes a patented Distributed Digital Calibration function similar to that of the XT Oscillator (Section 12.1.3.2). Because the LFRC Oscillator has a greater fundamental variability, the required range of calibration is much larger.
PAGE 526
Apollo3 Blue Datasheet 12.1.3.1 XT Oscillator Digital Calibration The XT Oscillator includes a Distributed Digital Calibration function. When the 32 kHz XT oscillator is selected, the clock at the 16 kHz level of the divider chain is modified on a selectable interval using the calibration value CALXT in the REG_CLKGEN_CALXT Register. Clock pulses are either added or subtracted to ensure accuracy of the XT.
PAGE 527
Apollo3 Blue Datasheet automatically adjusted by the Auto-adjustment function which is a combination of analog and digital operations. The HFRC is enabled only when it is required by an internal module. When the ARM core goes into a sleep mode, the HFRC will be disabled unless another module is using it. If the ARM core goes into deep sleep mode, the HFRC will be powered down when it is not needed.
PAGE 528
Apollo3 Blue Datasheet 12.1.6 Burst Mode Support The Apollo3 Blue MCU supports the TurboSPOT burst operating mode. Under burst mode, the core clock runs at 96MHz. Burst mode is initiated when the BURSTREQ bit in REG_CLK_GEN_FREQCTRL is written with a '1'. Once the burst mode is available, the BURSTACK and BURSTSTATUS bit in REG_CLK_GEN_FREQCTRL register are updated. When burst mode is no longer required, software will write a '0' to the BURSTREQ bit in REG_CLK_GEN_FREQCTRL.
PAGE 529
Apollo3 Blue Datasheet 12.1.8 Generating 100 Hz The Real Time Clock (RTC) module requires a 100 Hz clock which is provided by the Clock Generator. This clock may come either from the LFRC or the XT Oscillators, as determined by the REG_CLKGEN_OCTRL_OSEL bit. Since 100 Hz is not a simple power of two division of either of these oscillators, special functions are used to create it.
PAGE 530
Apollo3 Blue Datasheet 12.2.
PAGE 531
Apollo3 Blue Datasheet 12.2.2 CLKGEN Registers 12.2.2.1 CALXT Register XT Oscillator Control OFFSET: 0x00000000 INSTANCE 0 ADDRESS: 0x40004000 This is the XT Oscillator Calibration value. This value allows any derived XT clocks to be "calibrated". This means that the original 32KHz version of XT will not be changed, but a 16KHz version (divided down version) can be modified. This register value will add or subtract the number of cycles programmed in this register across a 32 seconds interval.
PAGE 532
Apollo3 Blue Datasheet Table 762: CALRC Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 RSVD 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CALRC Table 763: CALRC Register Bits Bit Name Reset RW 31:18 RSVD 0x0 RO 17:0 CALRC 0x0 RW Description RESERVED LFRC Oscillator calibration value.
PAGE 533
Apollo3 Blue Datasheet Table 765: ACALCTR Register Bits Bit Name 23:0 Reset ACALCTR RW 0x0 RO Description Autocalibration Counter result. Bits 17 down to 0 of this is feed directly to the CALRC register if ACAL register in OCTRL register is set to 1024SEC or 512SEC. 12.2.2.4 OCTRL Register Oscillator Control OFFSET: 0x0000000C INSTANCE 0 ADDRESS: 0x4000400C This register includes controls for autocalibration in addition to the RTC oscillator controls.
PAGE 534
Apollo3 Blue Datasheet Table 767: OCTRL Register Bits Bit Name Reset RW 5:2 RSVD 0x0 RO Description RESERVED Stop the LFRC Oscillator to the RTC 1 STOPRC 0x0 RW EN = 0x0 - Enable the LFRC Oscillator to drive the RTC STOP = 0x1 - Stop the LFRC Oscillator when driving the RTC Stop the XT Oscillator to the RTC 0 STOPXT 0x0 RW EN = 0x0 - Enable the XT Oscillator to drive the RTC STOP = 0x1 - Stop the XT Oscillator when driving the RTC 12.2.2.
PAGE 535
Apollo3 Blue Datasheet Table 769: CLKOUT Register Bits Bit Name Reset RW Description CLKOUT signal select LFRC = 0x0 - LFRC XT_DIV2 = 0x1 - XT / 2 XT_DIV4 = 0x2 - XT / 4 XT_DIV8 = 0x3 - XT / 8 XT_DIV16 = 0x4 - XT / 16 XT_DIV32 = 0x5 - XT / 32 RTC_1Hz = 0x10 - 1 Hz as selected in RTC XT_DIV2M = 0x16 - XT / 2^21 XT = 0x17 - XT CG_100Hz = 0x18 - 100 Hz as selected in CLKGEN 5:0 CKSEL 0x0 RW LFRC_DIV2 = 0x23 - LFRC / 2 LFRC_DIV32 = 0x24 - LFRC / 32 LFRC_DIV512 = 0x25 - LFRC / 512 LFRC_DIV32K = 0x26 -
PAGE 536
Apollo3 Blue Datasheet Table 770: CLKKEY Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CLKKEY Table 771: CLKKEY Register Bits Bit Name Reset RW 31:0 CLKKEY 0x0 RW Description Key register value. Key = 0x47 - Key 12.2.2.7 CCTRL Register HFRC Clock Control OFFSET: 0x00000018 INSTANCE 0 ADDRESS: 0x40004018 This register controls the main divider for HFRC clock.
PAGE 537
Apollo3 Blue Datasheet INSTANCE 0 ADDRESS: 0x4000401C This register provides status to the XT oscillator and the source of the RTC.
PAGE 538
Apollo3 Blue Datasheet Table 777: HFADJ Register Bits Bit Name Reset RW Description Gain control for HFRC adjustment 23:21 HFADJGAIN 0x1 RW Gain_of_1 = 0x0 - HF Adjust with Gain of 1 Gain_of_1_in_2 = 0x1 - HF Adjust with Gain of 0.5 Gain_of_1_in_4 = 0x2 - HF Adjust with Gain of 0.25 Gain_of_1_in_8 = 0x3 - HF Adjust with Gain of 0.125 Gain_of_1_in_16 = 0x4 - HF Adjust with Gain of 0.0625 Gain_of_1_in_32 = 0x5 - HF Adjust with Gain of 0.
PAGE 539
Apollo3 Blue Datasheet Table 779: CLOCKENSTAT Register Bits Bit Name Reset RW Description Clock enable status 31:0 CLOCKENSTAT 0x0 RO ADC_CLKEN = 0x1 - Clock enable for the ADC.
PAGE 540
Apollo3 Blue Datasheet Table 781: CLOCKEN2STAT Register Bits Bit Name Reset RW Description Clock enable status 2 CLOCKEN2STAT 31:0 0x0 RO IOMSTRIFC1_CLKEN = 0x1 - Clock enable for the IO MASTER 1 IFC INTERFACE IOMSTRIFC2_CLKEN = 0x2 - Clock enable for the IO MASTER 2 IFC INTERFACE IOMSTRIFC3_CLKEN = 0x4 - Clock enable for the IO MASTER 3 IFC INTERFACE IOMSTRIFC4_CLKEN = 0x8 - Clock enable for the IO MASTER 4 IFC INTERFACE IOMSTRIFC5_CLKEN = 0x10 - Clock enable for the IO MASTER 5 IFC INTERFACE PDM
PAGE 541
Apollo3 Blue Datasheet Table 783: CLOCKEN3STAT Register Bits Bit Name Reset RW Description Clock enable status 3 CLOCKEN3STAT 31:0 0x0 RO DAP_enabled = 0x20000 - DAP clock is enabled [17] VCOMP_enabled = 0x40000 - VCOMP powerdown indicator [18] XTAL_enabled = 0x1000000 - XTAL is enabled [24] HFRC_enabled = 0x2000000 - HFRC is enabled [25] HFADJEN = 0x4000000 - HFRC Adjust enabled [26] HFRC_en_out = 0x8000000 - HFRC Enabled out [27] RTC_XT = 0x10000000 - RTC use XT [28] clkout_xtal_en = 0x20000000
PAGE 542
Apollo3 Blue Datasheet 12.2.2.14BLEBUCKTONADJ Register BLE BUCK TON ADJUST OFFSET: 0x0000003C INSTANCE 0 ADDRESS: 0x4000403C This is the register control for BLE ton adjustment logic.
PAGE 543
Apollo3 Blue Datasheet Table 787: BLEBUCKTONADJ Register Bits Bit Name Reset RW Description BLEBUCK ZERO LENGTH DETECT TRIM 26:23 ZEROLENDETECTTRIM 0x0 RW SetF = 0xF - Indicator send when the BLE BUCK asserts blebuck_comp1 for about 81us (10 percent margin of error) or more SetE = 0xE - Indicator send when the BLE BUCK asserts blebuck_comp1 for about 75.6us (10 percent margin of error) or more SetD = 0xD - Indicator send when the BLE BUCK asserts blebuck_comp1 for about 70.
PAGE 544
Apollo3 Blue Datasheet Set bits in this register to allow this module to generate the corresponding interrupt.
PAGE 545
Apollo3 Blue Datasheet Table 791: INTRPTSTAT Register Bits Bit Name Reset RW 0 ACF 0x0 RW Description Autocalibration Fail interrupt 12.2.2.17INTRPTCLR Register CLKGEN Interrupt Register: Clear OFFSET: 0x00000108 INSTANCE 0 ADDRESS: 0x40004108 Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
PAGE 546
Apollo3 Blue Datasheet 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 RSVD 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ACF 3 0 ACC 3 1 OF Table 794: INTRPTSET Register Table 795: INTRPTSET Register Bits Bit Name Reset RW 31:3 RSVD 0x0 RO 2 OF 0x0 RW 1 ACC 0x0 RW 0 ACF 0x0 RW DS-A3-0p9p1 Description RESERVED XT Oscillator Fail interrupt Autocalibration Complete interrupt Autocalibration Fail interrupt Page 546 of 909 20
PAGE 547
Apollo3 Blue Datasheet 12.3 Real Time Clock 100Hz 100ths Ctr Secs Ctr Mins Ctr Hours Ctr Date Ctr Month Ctr Cmpr Cmpr Cmpr Cmpr Cmpr Cmpr 100ths Alm Secs Alm Mins Alm Hours Alm Date Alm Month Alm Year Ctr Int Logic Wkdy Ctr Cmpr Wkdy Alm Figure 65. Block diagram for the Real Time Clock Module 12.3.1 RTC Functional Overview The Real Time Clock (RTC) Module, shown in Figure 65, provides an accurate real time measurement.
PAGE 548
Apollo3 Blue Datasheet 12.3.4 Alarms There are seven Alarm Registers which may be used to generate an Alarm interrupt at a specific time. These registers correspond to the 100th of a second (REG_CLK_GEN_ALMLOW_ALM100), second (REG_CLK_GEN_ALMLOW_ALMSEC), minute (REG_CLK_GEN_ALMLOW_ALMMIN), hour (REG_CLK_GEN_ALMLOW_ALMHR), day of the month (REG_CLK_GEN_ALMUP_ALMDATE), day of the week (REG_CLK_GEN_ALMUP_ALMWKDY) and month (REG_CLK_GEN_ALMUP_ALMMO) Calendar Counters.
PAGE 549
Apollo3 Blue Datasheet 12.3.7 Weekday Function The Weekday Counter is simply a 3-bit counter which counts up to 6 and then resets to 0. It is the responsibility of software to assign particular days of the week to each counter value. 12.4 RTC Registers Real Time Clock INSTANCE 0 BASE ADDRESS:0x40004200 12.4.
PAGE 550
Apollo3 Blue Datasheet 12.4.2 RTC Registers 12.4.2.1 CTRLOW Register RTC Counters Lower OFFSET: 0x00000040 INSTANCE 0 ADDRESS: 0x40004240 This counter contains the values for hour, minutes, seconds and 100ths of a second Counter.
PAGE 551
Apollo3 Blue Datasheet Table 800: CTRUP Register 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 CTRYR 1 4 RSVD 1 3 1 2 1 1 1 0 0 9 0 8 CTRMO 0 7 0 6 RSVD 2 7 CTRWKDY 2 8 CB RSVD 2 9 CEB 3 0 CTERR 3 1 0 5 0 4 0 3 0 2 0 1 0 0 CTRDATE Table 801: CTRUP Register Bits Bit 31 Name CTERR Reset 0x0 RW RO Description Counter read error status.
PAGE 552
Apollo3 Blue Datasheet This register is the Alarm settings for hours, minutes, second and 1/100th seconds settings.
PAGE 553
Apollo3 Blue Datasheet Table 805: ALMUP Register Bits Bit Name Reset RW 31:19 RSVD 0x0 RO 18:16 ALMWKDY 0x0 RW 15:13 RSVD 0x0 RO 12:8 ALMMO 0x0 RW 7:6 RSVD 0x0 RO 5:0 ALMDATE 0x0 RW Description RESERVED Weekdays Alarm RESERVED Months Alarm RESERVED Date Alarm 12.4.2.5 RTCCTL Register RTC Control Register OFFSET: 0x00000050 INSTANCE 0 ADDRESS: 0x40004250 This is the register control for the RTC module.
PAGE 554
Apollo3 Blue Datasheet Table 807: RTCCTL Register Bits Bit Name Reset RW Description Alarm repeat interval 3:1 RPT 0x0 RW DIS = 0x0 - Alarm interrupt disabled YEAR = 0x1 - Interrupt every year MONTH = 0x2 - Interrupt every month WEEK = 0x3 - Interrupt every week DAY = 0x4 - Interrupt every day HR = 0x5 - Interrupt every hour MIN = 0x6 - Interrupt every minute SEC = 0x7 - Interrupt every second/10th/100th Counter write control 0 WRTC 0x0 RW DIS = 0x0 - Counter writes are disabled EN = 0x1 - Co
PAGE 555
Apollo3 Blue Datasheet Table 810: INTSTAT Register 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ALM 3 1 RSVD Table 811: INTSTAT Register Bits Bit Name Reset RW 31:1 RSVD 0x0 RO 0 ALM 0x0 RW Description RESERVED RTC Alarm interrupt 12.4.2.
PAGE 556
Apollo3 Blue Datasheet Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
PAGE 557
Apollo3 Blue Datasheet 13. Counter/Timer Module CLRA CLRB TMRPINB TMRPINA 16-bit Counter A 16-bit Counter B Clk Sources 16-bit Compare0/1/2/3A 16-bit Compare0/1/2/3B Cmprs Patsel Cmprs Patsel ConfigurationA ConfigurationB TMRAOUT TRIGGERA TMRAOUT2 TRIGGERB Control TMRINTA TMRBOUT TMRBOUT2 TMRINTB TMRINTA TMRINTB Figure 66. Block Diagram for One Counter/Timer Pair 13.
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Apollo3 Blue Datasheet ▪ Generate outputs triggered or terminated by outputs of other Timer/Counters ▪ Generate a specified number of patterns ▪ Special inversion functions to support bidirectional stepper motor patterns 13.2 Counter/Timer Functions Each Counter/Timer operates in a mode controlled by the REG_CTIMER_CTCTRLx_TMRxyFN bit field (x=0 to 7, y=A or B). The mode affects both the generation of interrupts and the control of the outputs. Each mode is described in the following sections.
PAGE 559
Apollo3 Blue Datasheet 13.2.2 Repeated Count (FN = 1) Operation in this mode is shown in Figure 68. When the Timer is enabled, the pin output is at the level selected by the POL bit and the Timer is at zero because REG_CTIMER_TMRxyCLR has been asserted previously. The Timer counts up on each selected clock, and when it reaches the value in the corresponding CMPR0 Register the output pin switches polarity (if the REG_CTIMER_TMRxyPE bit is set) and an interrupt is generated (if the IE bit is set).
PAGE 560
Apollo3 Blue Datasheet ~CMPR1 + 2 ~CMPR0 + 2 Out (POL = 0) Out (POL = 1) INT Counter 0 Incrementing 0 EN Figure 69. Counter/Timer Operation, FN = 2 The normal interrupt is generated on the rising edge of the output (before polarity is applied) if IE0 is set, as shown in Counter/Timer Operation, FN = 2Figure 69. The secondary interrupt is generated on the falling edge of the output if the REG_CTIMER_TMRxyIE1 bit is set. 13.2.4 Repeated Pulse (FN = 3) Operation in this mode is shown in Figure 70.
PAGE 561
Apollo3 Blue Datasheet The normal interrupt is generated on the rising edge of the output (before polarity is applied) if IE0 is set, as shown in Counter/Timer Operation, FN = 3Figure 70. The secondary interrupt is generated on the falling edge of the output if the IE1 bit is set. 13.2.5 Single Pattern (FN = 4) In this mode the CTIMER outputs are generated from the pattern in the CMPR0/1/2/3 registers rather than from comparisons to the Counter. The Counter is still used to step through the pattern bits.
PAGE 562
Apollo3 Blue Datasheet OUT LMT + 1 LMT + 1 LMT + 1 PATTERN PATTERN PATTERN PAT INT Counter 0 Incrementing 0 Incrementing 0 Incrementing 0 Inc EN Figure 72. Counter/Timer Operation, FN = 5 The primary interrupt is generated when the pattern rolls over to 0 (if IE0 is set). If LMT is greater than 31 and less than 63, the secondary interrupt will be generated when the Counter increments to 32 (if IE1 is set).
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Apollo3 Blue Datasheet LMT + 1 OUT PATTERN INT Counter 0 INCREMENTING 0 EN Figure 73. Counter/Timer Operation, FN = 4 13.2.8 Alternate Pulse (FN = 7) Operation in this mode is shown in Figure 74, and is very similar to Repeated Pulse mode (FN = 3). The only difference is that at the end of each cycle, the comparison register switch between CMPR0/1 and CMPR2/3. This can be used to create a more complex stream of pulses, and may also be used to support an efficient software controlled audio output.
PAGE 564
Apollo3 Blue Datasheet 13.4 Creating a Secondary Output with CMPR2/3 In any of the Count or Pulse modes (FN = 0, 1, 2 or 3), the REG_CTIMER_CMPR2 and REG_CTIMER_CMPR3 registers provide two additional comparison points. When the counter reaches a value in either CMPR2 or CMPR3, the secondary output OUT2 is toggled. This allows the creation of complex combinations of the two outputs, as shown in Complex Operations with CMPR2 and CMPR3.
PAGE 565
Apollo3 Blue Datasheet LMT + 1 LMT + 1 LMT + 1 OUT PATTERN01 PATTERN01 PATTERN01 OUT2 PATTERN23 PATTERN23 PATTERN23 INT Counter 0 Incrementing 0 Incrementing 0 Incrementing 0 Inc EN Figure 76. Dual Pattern Generation 13.6 Synchronized A/B Patterns If the CTLINK bit is set for the B timer of a pair when a Pattern mode is selected (FN = 4 or 5), the pattern comparison value is taken from the A Counter rather than the B Counter.
PAGE 566
Apollo3 Blue Datasheet burst of pulses or patterns of a specified length. This is shown in Figure 78 for the case of Repeat Pulse mode. In this case the TRIG signal is the output of a TIMER configured in Single Pulse mode (FN = 2) with the time configured to be somewhat more than 3 times the pulse repeat. When the TRIG signal occurs, the pulse output is terminated at the end of the current cycle. OUT TRIG EN Figure 78. Terminated Repeat Patterns 13.7.
PAGE 567
Apollo3 Blue Datasheet mode. Two counters are configured with FN = 6 so that they count continuously. One is supplied HCLK as its clock, and the other is supplied with a divided version of the HFRC clock. The two counters are enabled simultaneously, and after some period of system operation they are disabled and read.
PAGE 568
Apollo3 Blue Datasheet 13.15Pattern-based Sine Wave Examples Some applications, such as driving the Linear Resonance Actuator (LRA) in a Haptic Driver or vibrator, require the generation of a pattern which is integrated into an analog signal, most commonly as a sine wave. Figure 79 shows the typical function. The square pulses have variable duty cycles, and they are integrated by the external device to produce the sine wave.
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Apollo3 Blue Datasheet Fast_clk PWM Out PWM Period CMPR0 + Intrpt PWM Period PWM Period PWM Period PWM Period PWM Period PWM Period CMPR2 + Intrpt CMPR0 + Intrpt CMPR2 + Intrpt CMPR0 + Intrpt CMPR2 + Intrpt CMPR0 + Intrpt CMPR1 CMPR3 CMPR1 CMPR3 CMPR1 CMPR3 PWM Period CMPR2 + Intrpt CMPR1 CMPR3 Figure 80. PWM-based Pulse Train 13.15.2Pattern-based Pulse Trains The pulse patterns may also be generated using the Repeated Pattern function described in Section 13.2.6.
PAGE 570
Apollo3 Blue Datasheet EN is used to enable (when 1) and disable (when 0) the counting function of the CTIMER. However, EN and the deassertion of CLR are synchronized to the selected clock, which must be accounted for when they are used. CLR and EN Operation shows how this synchronization occurs. When CLR is set to 0, the Counter will begin counting on the second edge of the selected clock if EN is set to 1.
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Apollo3 Blue Datasheet 13.18.2Counting Buck Converter Edges Apollo3 includes three separate buck converters which provide power for the Processor power domain (BUCKA), the Memory power domain (BUCKB) and the BLE interface module (BUCKBLE). Each CTIMER may be connected to a pulse stream from any of the three analog Buck Converters.
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Apollo3 Blue Datasheet 13.20Pad Connections from the Timer/Counter In order to provide flexibility in connecting timers to external devices, a secondary multiplexing mechanism is provided for the timer outputs. There are 32 pads which can be configured for either inputs to or outputs from the Timer/Counter module. Each of these pads can be driven by one of four outputs selected by the REG_CTIMER_OUTCFG0/1/2/3 registers, as shown in Table 818.
PAGE 573
Apollo3 Blue Datasheet Table 816: Counter/Timer Pad Configuration DS-A3-0p9p1 Field Value Ctr/Timer Pad PAD12FNCSEL 2 A0 12 PAD25FNCSEL 2 A0 25 PAD42FNCSEL 2 A0 42 PAD13FNCSEL 2 B0 13 PAD26FNCSEL 2 B0 26 PAD43FNCSEL 2 B0 43 PAD18FNCSEL 2 A1 18 PAD27FNCSEL 2 A1 27 PAD44FNCSEL 2 A1 44 PAD19FNCSEL 2 B1 19 PAD28FNCSEL 2 B1 28 PAD45FNCSEL 2 B1 45 PAD20FNCSEL 2 A2 20 PAD29FNCSEL 2 A2 29 PAD46FNCSEL 2 A2 46 PAD21FNCSEL 2 B2 21 PAD30FNCSEL 2 B
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Apollo3 Blue Datasheet Table 817: Counter/Timer Pad Configuration DS-A3-0p9p1 Field Value Ctr/Timer Pad PAD12FNCSEL 2 A0 12 PAD25FNCSEL 2 A0 25 PAD42FNCSEL 2 A0 42 PAD13FNCSEL 2 B0 13 PAD26FNCSEL 2 B0 26 PAD43FNCSEL 2 B0 43 PAD18FNCSEL 2 A1 18 PAD19FNCSEL 4 A1 19 PAD24FNCSEL 5 A1 24 PAD26FNCSEL 5 A1 26 PAD27FNCSEL 2 A1 27 PAD35FNCSEL 5 A1 35 PAD37FNCSEL 7 A1 37 PAD44FNCSEL 2 A1 44 PAD45FNCSEL 7 A1 45 PAD46FNCSEL 4 A1 46 PAD19FNCSEL 2 B
PAGE 575
Apollo3 Blue Datasheet Table 818: Counter/Timer Pad Configuration Pad (FNCSEL) ctimer output signal Output Selection (REG_CTIMER_INCFG) 0 1 2 3 4 5 6 7 PAD4 (6) CT17 Force to 0 Force to 1 A4OUT2 B7OUT A4OUT A1OUT2 A6OUT2 A7OUT2 PAD5 (7) CT8 Force to 0 Force to 1 A2OUT A3OUT2 A4OUT2 B6OUT A6OUT2 A7OUT2 PAD6 (5) CT10 Force to 0 Force to 1 B2OUT B3OUT2 B4OUT2 A6OUT A6OUT2 A7OUT2 PAD7 (7) CT19 Force to 0 Force to 1 B4OUT2 A2OUT B4OUT B1OUT2 A6OUT2 A7OUT2 PAD11
PAGE 576
Apollo3 Blue Datasheet Table 818: Counter/Timer Pad Configuration Pad (FNCSEL) ctimer output signal Output Selection (REG_CTIMER_INCFG) 0 1 2 3 4 5 6 7 PAD37 (7) CT29 Force to 0 Force to 1 B5OUT2 A1OUT A7OUT A3OUT2 A6OUT2 A7OUT2 PAD39 (2) CT25 Force to 0 Force to 1 B4OUT2 B2OUT A6OUT A2OUT2 A6OUT2 A7OUT2 PAD42 (2) CT16 Force to 0 Force to 1 A4OUT A0OUT A0OUT2 B3OUT2 A6OUT2 A7OUT2 PAD43 (2) CT18 Force to 0 Force to 1 B4OUT B0OUT A0OUT A3OUT2 A6OUT2 A7OUT2 PA
PAGE 577
Apollo3 Blue Datasheet Note that for the Pulse and Count modes, the CMPR2/3 registers can always be configured so that OUT2 matches OUT. This provides more flexibility in the pin assignments, as any OUT2 connection can be used as the corresponding OUT function if a separate OUT2 function is not required. For a single 32-bit pattern from a timer, OUT2 can be configured in the CMPR2/3 registers to produce the same pattern as OUT.
PAGE 578
Apollo3 Blue Datasheet 13.21.
PAGE 579
Apollo3 Blue Datasheet Table 820: CTIMER Register Map Address(s) DS-A3-0p9p1 Register Name Description 0x400080A4 CMPRA5 Counter/Timer A5 Compare Registers 0x400080A8 CMPRB5 Counter/Timer B5 Compare Registers 0x400080AC CTRL5 Counter/Timer Control 0x400080B4 CMPRAUXA5 Counter/Timer A5 Compare Registers 0x400080B8 CMPRAUXB5 Counter/Timer B5 Compare Registers 0x400080BC AUX5 Counter/Timer Auxiliary 0x400080C0 TMR6 Counter/Timer Register 0x400080C4 CMPRA6 Counter/Timer A6 Compare Re
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Apollo3 Blue Datasheet 13.21.2CTIMER Registers 13.21.2.1TMR0 Register Counter/Timer Register OFFSET: 0x00000000 INSTANCE 0 ADDRESS: 0x40008000 This register holds the running time or event count for ctimer 0. This is either for each 16 bit half or for the whole 32 bit count when the pair is linked. If the pair is not linked, they can be running on seperate clocks and are completely independent.
PAGE 581
Apollo3 Blue Datasheet Table 824: CMPRA0 Register Bits Bit Name Reset RW Description 31:16 CMPR1A0 0x0 RW Counter/Timer A0 Compare Register 1. Holds the upper limit for timer half A. 15:0 CMPR0A0 0x0 RW Counter/Timer A0 Compare Register 0. Holds the lower limit for timer half A. 13.21.2.3CMPRB0 Register Counter/Timer B0 Compare Registers OFFSET: 0x00000008 INSTANCE 0 ADDRESS: 0x40008008 This contains the Compare limits for timer 0 B half.
PAGE 582
Apollo3 Blue Datasheet 2 0 1 9 1 8 1 7 TMRB0CLK 1 6 1 5 1 4 RSVD 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 TMRA0CLK 0 1 0 0 TMRA0EN 2 1 TMRA0FN 2 2 TMRA0IE0 2 3 TMRA0IE1 TMRB0IE0 2 4 TMRA0CLR 2 5 TMRA0POL 2 6 TMRB0EN 2 7 TMRB0FN 2 8 TMRB0IE1 RSVD 2 9 TMRB0CLR 3 0 CTLINK0 3 1 TMRB0POL Table 827: CTRL0 Register Table 828: CTRL0 Register Bits Bit Name Reset RW Description Counter/Timer A0/B0 Link bit.
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Apollo3 Blue Datasheet Table 828: CTRL0 Register Bits Bit Name Reset RW Description Counter/Timer B0 Function Select. 24:22 TMRB0FN 0x0 RW SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B0, stop. REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B0, restart. PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B0, assert, count to CMPR1B0, deassert, stop. PULSE_CONT = 0x3 - Pulse continously.
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Apollo3 Blue Datasheet Table 828: CTRL0 Register Bits Bit Name Reset RW Description Counter/Timer A0 output polarity. 12 TMRA0POL 0x0 RW NORMAL = 0x0 - The polarity of the TMRPINA0 pin is the same as the timer output. INVERTED = 0x1 - The polarity of the TMRPINA0 pin is the inverse of the timer output. Counter/Timer A0 Clear bit. 11 TMRA0CLR 0x0 RW RUN = 0x0 - Allow counter/timer A0 to run CLEAR = 0x1 - Holds counter/timer A0 at 0x0000. Counter/Timer A0 Interrupt Enable bit based on COMPR1.
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Apollo3 Blue Datasheet Table 828: CTRL0 Register Bits Bit Name Reset RW Description Counter/Timer A0 Clock Select. 5:1 TMRA0CLK 0x0 RW TMRPIN = 0x0 - Clock source is TMRPINA. HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4 HFRC_DIV16 = 0x2 - Clock source is HFRC / 16 HFRC_DIV256 = 0x3 - Clock source is HFRC / 256 HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated).
PAGE 586
Apollo3 Blue Datasheet Table 830: CMPRAUXA0 Register Bits Bit Name Reset RW Description 31:16 CMPR3A0 0x0 RW Counter/Timer A0 Compare Register 3. Holds the upper limit for timer half A. 15:0 CMPR2A0 0x0 RW Counter/Timer A0 Compare Register 2. Holds the lower limit for timer half A. 13.21.2.6CMPRAUXB0 Register Counter/Timer B0 Compare Registers OFFSET: 0x00000018 INSTANCE 0 ADDRESS: 0x40008018 Enhanced compare limits for timer half B.
PAGE 587
Apollo3 Blue Datasheet 2 1 2 0 1 9 1 8 1 7 TMRB0LMT 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 TMRA0TRIG 2 2 TMRA0NOSYNC 2 3 TMRA0TINV 2 4 TMRA0POL23 2 5 TMRA0EN23 2 6 RSVD TMRB0POL23 2 7 RSVD RSVD 2 8 TMRB0TRIG 2 9 TMRB0TINV 3 0 TMRB0NOSYNC 3 1 TMRB0EN23 Table 833: AUX0 Register 0 4 0 3 0 2 0 1 0 0 TMRA0LMT Table 834: AUX0 Register Bits Bit Name Reset RW 31 RSVD 0x0 RO Description RESERVED Counter/Timer B0 Upper compare enable.
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Apollo3 Blue Datasheet Table 834: AUX0 Register Bits Bit Name Reset RW 21:16 TMRB0LMT 0x0 RW 15 RSVD 0x0 RO Description Counter/Timer B0 Pattern Limit Count. RESERVED Counter/Timer A0 Upper compare enable. 14 TMRA0EN23 0x0 RW DIS = 0x1 - Disable enhanced functions. EN = 0x0 - Enable enhanced functions. Counter/Timer A0 Upper output polarity 13 TMRA0POL23 0x0 RW NORM = 0x0 - Upper output normal polarity INV = 0x1 - Upper output inverted polarity. Counter/Timer A0 Invert on trigger.
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Apollo3 Blue Datasheet Table 835: TMR1 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 CTTMRB1 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CTTMRA1 Table 836: TMR1 Register Bits Bit Name Reset RW 31:16 CTTMRB1 0x0 RO 15:0 CTTMRA1 0x0 RO Description Counter/Timer B1. Counter/Timer A1. 13.21.2.
PAGE 590
Apollo3 Blue Datasheet Table 839: CMPRB1 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 CMPR1B1 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMPR0B1 Table 840: CMPRB1 Register Bits Bit Name Reset RW 31:16 CMPR1B1 0x0 RW 15:0 CMPR0B1 0x0 RW Description Counter/Timer B1 Compare Register 1. Counter/Timer B1 Compare Register 0. 13.21.2.
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Apollo3 Blue Datasheet Table 842: CTRL1 Register Bits Bit Name Reset RW Description Counter/Timer B1 output polarity. 28 TMRB1POL 0x0 RW NORMAL = 0x0 - The polarity of the TMRPINB1 pin is the same as the timer output. INVERTED = 0x1 - The polarity of the TMRPINB1 pin is the inverse of the timer output. Counter/Timer B1 Clear bit. 27 TMRB1CLR 0x0 RW RUN = 0x0 - Allow counter/timer B1 to run CLEAR = 0x1 - Holds counter/timer B1 at 0x0000. Counter/Timer B1 Interrupt Enable bit for COMPR1.
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Apollo3 Blue Datasheet Table 842: CTRL1 Register Bits Bit Name Reset RW Description Counter/Timer B1 Clock Select. 21:17 TMRB1CLK 0x0 RW TMRPIN = 0x0 - Clock source is TMRPINB. HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4 HFRC_DIV16 = 0x2 - Clock source is HFRC / 16 HFRC_DIV256 = 0x3 - Clock source is HFRC / 256 HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated).
PAGE 593
Apollo3 Blue Datasheet Table 842: CTRL1 Register Bits Bit Name Reset RW Description Counter/Timer A1 Interrupt Enable bit based on COMPR0. 9 TMRA1IE0 0x0 RW DIS = 0x0 - Disable counter/timer A1 from generating an interrupt based on COMPR0. EN = 0x1 - Enable counter/timer A1 to generate an interrupt based on COMPR0. Counter/Timer A1 Function Select. 8:6 TMRA1FN 0x0 RW SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A1, stop.
PAGE 594
Apollo3 Blue Datasheet Table 842: CTRL1 Register Bits Bit Name Reset RW Description Counter/Timer A1 Enable bit. 0 TMRA1EN 0x0 RW DIS = 0x0 - Counter/Timer A1 Disable. EN = 0x1 - Counter/Timer A1 Enable. 13.21.2.12CMPRAUXA1 Register Counter/Timer A1 Compare Registers OFFSET: 0x00000034 INSTANCE 0 ADDRESS: 0x40008034 Enhanced compare limits for timer half A. This is valid if timer 1 is set to function 4 and function 5.
PAGE 595
Apollo3 Blue Datasheet Table 846: CMPRAUXB1 Register Bits Bit Name Reset RW Description 31:16 CMPR3B1 0x0 RW Counter/Timer B1 Compare Register 3. Holds the upper limit for timer half B. 15:0 CMPR2B1 0x0 RW Counter/Timer B1 Compare Register 2. Holds the lower limit for timer half B. 13.21.2.14AUX1 Register Counter/Timer Auxiliary OFFSET: 0x0000003C INSTANCE 0 ADDRESS: 0x4000803C Control bit fields for both halves of timer 0.
PAGE 596
Apollo3 Blue Datasheet Table 848: AUX1 Register Bits Bit Name 27 TMRB1NOSYNC Reset RW Description Source clock synchronization control. 0x0 RW DIS = 0x0 - Synchronization on source clock NOSYNC = 0x1 - No synchronization on source clock Counter/Timer B1 Trigger Select. 26:23 TMRB1TRIG 0x0 RW 22 RSVD 0x0 RO 21:16 TMRB1LMT 0x0 RW 15 RSVD 0x0 RO DIS = 0x0 - Trigger source is disabled. A1OUT = 0x1 - Trigger source is CTIMERA1 OUT. B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.
PAGE 597
Apollo3 Blue Datasheet Table 848: AUX1 Register Bits Bit Name Reset RW Description Counter/Timer A1 Trigger Select. 10:7 TMRA1TRIG 0x0 RW 6:0 TMRA1LMT 0x0 RW DIS = 0x0 - Trigger source is disabled. B1OUT = 0x1 - Trigger source is CTIMERB1 OUT. B3OUT = 0x2 - Trigger source is CTIMERB3 OUT. A3OUT = 0x3 - Trigger source is CTIMERA3 OUT. A0OUT = 0x4 - Trigger source is CTIMERA0 OUT. B0OUT = 0x5 - Trigger source is CTIMERB0 OUT. A5OUT = 0x6 - Trigger source is CTIMERA5 OUT.
PAGE 598
Apollo3 Blue Datasheet 13.21.2.16CMPRA2 Register Counter/Timer A2 Compare Registers OFFSET: 0x00000044 INSTANCE 0 ADDRESS: 0x40008044 This register holds the compare limits for timer 2 A half.
PAGE 599
Apollo3 Blue Datasheet 13.21.2.18CTRL2 Register Counter/Timer Control OFFSET: 0x0000004C INSTANCE 0 ADDRESS: 0x4000804C This register holds the control bit fields for both halves of timer 2.
PAGE 600
Apollo3 Blue Datasheet Table 856: CTRL2 Register Bits Bit Name Reset RW Description Counter/Timer B2 Function Select. 24:22 TMRB2FN 0x0 RW SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B2, stop. REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B2, restart. PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B2, assert, count to CMPR1B2, deassert, stop. PULSE_CONT = 0x3 - Pulse continously.
PAGE 601
Apollo3 Blue Datasheet Table 856: CTRL2 Register Bits Bit Name Reset RW Description Counter/Timer A2 output polarity. 12 TMRA2POL 0x0 RW NORMAL = 0x0 - The polarity of the TMRPINA2 pin is the same as the timer output. INVERTED = 0x1 - The polarity of the TMRPINA2 pin is the inverse of the timer output. Counter/Timer A2 Clear bit. 11 TMRA2CLR 0x0 RW RUN = 0x0 - Allow counter/timer A2 to run CLEAR = 0x1 - Holds counter/timer A2 at 0x0000. Counter/Timer A2 Interrupt Enable bit based on COMPR1.
PAGE 602
Apollo3 Blue Datasheet Table 856: CTRL2 Register Bits Bit Name Reset RW Description Counter/Timer A2 Clock Select. 5:1 TMRA2CLK 0x0 RW TMRPIN = 0x0 - Clock source is TMRPINA. HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4 HFRC_DIV16 = 0x2 - Clock source is HFRC / 16 HFRC_DIV256 = 0x3 - Clock source is HFRC / 256 HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated).
PAGE 603
Apollo3 Blue Datasheet Table 858: CMPRAUXA2 Register Bits Bit Name Reset RW Description 31:16 CMPR3A2 0x0 RW Counter/Timer A2 Compare Register 3. Holds the upper limit for timer half A. 15:0 CMPR2A2 0x0 RW Counter/Timer A2 Compare Register 2. Holds the lower limit for timer half A. 13.21.2.20CMPRAUXB2 Register Counter/Timer B2 Compare Registers OFFSET: 0x00000058 INSTANCE 0 ADDRESS: 0x40008058 Enhanced compare limits for timer half B.
PAGE 604
Apollo3 Blue Datasheet 2 1 2 0 1 9 1 8 1 7 TMRB2LMT 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 TMRA2TRIG 2 2 TMRA2NOSYNC 2 3 TMRA2TINV 2 4 TMRA2POL23 2 5 TMRA2EN23 2 6 RSVD TMRB2POL23 2 7 RSVD RSVD 2 8 TMRB2TRIG 2 9 TMRB2TINV 3 0 TMRB2NOSYNC 3 1 TMRB2EN23 Table 861: AUX2 Register 0 4 0 3 0 2 0 1 0 0 TMRA2LMT Table 862: AUX2 Register Bits Bit Name Reset RW 31 RSVD 0x0 RO Description RESERVED Counter/Timer B2 Upper compare enable.
PAGE 605
Apollo3 Blue Datasheet Table 862: AUX2 Register Bits Bit Name Reset RW 21:16 TMRB2LMT 0x0 RW 15 RSVD 0x0 RO Description Counter/Timer B2 Pattern Limit Count. RESERVED Counter/Timer A2 Upper compare enable. 14 TMRA2EN23 0x0 RW DIS = 0x1 - Disable enhanced functions. EN = 0x0 - Enable enhanced functions. Counter/Timer A2 Upper output polarity 13 TMRA2POL23 0x0 RW NORM = 0x0 - Upper output normal polarity INV = 0x1 - Upper output inverted polarity. Counter/Timer A2 Invert on trigger.
PAGE 606
Apollo3 Blue Datasheet Table 863: TMR3 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 CTTMRB3 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CTTMRA3 Table 864: TMR3 Register Bits Bit Name Reset RW 31:16 CTTMRB3 0x0 RO 15:0 CTTMRA3 0x0 RO Description Counter/Timer B3. Counter/Timer A3. 13.21.2.
PAGE 607
Apollo3 Blue Datasheet Table 867: CMPRB3 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 CMPR1B3 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMPR0B3 Table 868: CMPRB3 Register Bits Bit Name Reset RW 31:16 CMPR1B3 0x0 RW 15:0 CMPR0B3 0x0 RW Description Counter/Timer B3 Compare Register 1. Counter/Timer B3 Compare Register 0. 13.21.2.
PAGE 608
Apollo3 Blue Datasheet Table 870: CTRL3 Register Bits Bit Name Reset RW Description Counter/Timer B3 output polarity. 28 TMRB3POL 0x0 RW NORMAL = 0x0 - The polarity of the TMRPINB3 pin is the same as the timer output. INVERTED = 0x1 - The polarity of the TMRPINB3 pin is the inverse of the timer output. Counter/Timer B3 Clear bit. 27 TMRB3CLR 0x0 RW RUN = 0x0 - Allow counter/timer B3 to run CLEAR = 0x1 - Holds counter/timer B3 at 0x0000. Counter/Timer B3 Interrupt Enable bit for COMPR1.
PAGE 609
Apollo3 Blue Datasheet Table 870: CTRL3 Register Bits Bit Name Reset RW Description Counter/Timer B3 Clock Select. 21:17 TMRB3CLK 0x0 RW TMRPIN = 0x0 - Clock source is TMRPINB. HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4 HFRC_DIV16 = 0x2 - Clock source is HFRC / 16 HFRC_DIV256 = 0x3 - Clock source is HFRC / 256 HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated).
PAGE 610
Apollo3 Blue Datasheet Table 870: CTRL3 Register Bits Bit Name Reset RW Description Counter/Timer A3 Interrupt Enable bit based on COMPR1. 10 TMRA3IE1 0x0 RW DIS = 0x0 - Disable counter/timer A3 from generating an interrupt based on COMPR1. EN = 0x1 - Enable counter/timer A3 to generate an interrupt based on COMPR1. Counter/Timer A3 Interrupt Enable bit based on COMPR0. 9 TMRA3IE0 0x0 RW DIS = 0x0 - Disable counter/timer A3 from generating an interrupt based on COMPR0.
PAGE 611
Apollo3 Blue Datasheet Table 870: CTRL3 Register Bits Bit Name Reset RW Description Counter/Timer A3 Clock Select. 5:1 TMRA3CLK 0x0 RW TMRPIN = 0x0 - Clock source is TMRPINA. HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4 HFRC_DIV16 = 0x2 - Clock source is HFRC / 16 HFRC_DIV256 = 0x3 - Clock source is HFRC / 256 HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated).
PAGE 612
Apollo3 Blue Datasheet Table 872: CMPRAUXA3 Register Bits Bit Name Reset RW Description 31:16 CMPR3A3 0x0 RW Counter/Timer A3 Compare Register 3. Holds the upper limit for timer half A. 15:0 CMPR2A3 0x0 RW Counter/Timer A3 Compare Register 2. Holds the lower limit for timer half A. 13.21.2.27CMPRAUXB3 Register Counter/Timer B3 Compare Registers OFFSET: 0x00000078 INSTANCE 0 ADDRESS: 0x40008078 Enhanced compare limits for timer half B.
PAGE 613
Apollo3 Blue Datasheet 2 1 2 0 1 9 1 8 1 7 TMRB3LMT 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 TMRA3TRIG 2 2 TMRA3NOSYNC 2 3 TMRA3TINV 2 4 TMRA3POL23 2 5 TMRA3EN23 2 6 RSVD TMRB3POL23 2 7 RSVD RSVD 2 8 TMRB3TRIG 2 9 TMRB3TINV 3 0 TMRB3NOSYNC 3 1 TMRB3EN23 Table 875: AUX3 Register 0 4 0 3 0 2 0 1 0 0 TMRA3LMT Table 876: AUX3 Register Bits Bit Name Reset RW 31 RSVD 0x0 RO Description RESERVED Counter/Timer B3 Upper compare enable.
PAGE 614
Apollo3 Blue Datasheet Table 876: AUX3 Register Bits Bit Name Reset RW 21:16 TMRB3LMT 0x0 RW 15 RSVD 0x0 RO Description Counter/Timer B3 Pattern Limit Count. RESERVED Counter/Timer A3 Upper compare enable. 14 TMRA3EN23 0x0 RW DIS = 0x1 - Disable enhanced functions. EN = 0x0 - Enable enhanced functions. Counter/Timer A3 Upper output polarity 13 TMRA3POL23 0x0 RW NORM = 0x0 - Upper output normal polarity INV = 0x1 - Upper output inverted polarity. Counter/Timer A3 Invert on trigger.
PAGE 615
Apollo3 Blue Datasheet Table 877: TMR4 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 CTTMRB4 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CTTMRA4 Table 878: TMR4 Register Bits Bit Name Reset RW 31:16 CTTMRB4 0x0 RO 15:0 CTTMRA4 0x0 RO Description Counter/Timer B4. Counter/Timer A4. 13.21.2.
PAGE 616
Apollo3 Blue Datasheet Table 881: CMPRB4 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 CMPR1B4 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMPR0B4 Table 882: CMPRB4 Register Bits Bit Name Reset RW Description 31:16 CMPR1B4 0x0 RW Counter/Timer B4 Compare Register 1. Holds the upper limit for timer half B. 15:0 CMPR0B4 0x0 RW Counter/Timer B4 Compare Register 0. Holds the lower limit for timer half B. 13.21.2.
PAGE 617
Apollo3 Blue Datasheet Table 884: CTRL4 Register Bits Bit Name Reset RW Description Counter/Timer B4 output polarity. 28 TMRB4POL 0x0 RW NORMAL = 0x0 - The polarity of the TMRPINB4 pin is the same as the timer output. INVERTED = 0x1 - The polarity of the TMRPINB4 pin is the inverse of the timer output. Counter/Timer B4 Clear bit. 27 TMRB4CLR 0x0 RW RUN = 0x0 - Allow counter/timer B4 to run CLEAR = 0x1 - Holds counter/timer B4 at 0x0000. Counter/Timer B4 Interrupt Enable bit for COMPR1.
PAGE 618
Apollo3 Blue Datasheet Table 884: CTRL4 Register Bits Bit Name Reset RW Description Counter/Timer B4 Clock Select. 21:17 TMRB4CLK 0x0 RW TMRPIN = 0x0 - Clock source is TMRPINB. HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4 HFRC_DIV16 = 0x2 - Clock source is HFRC / 16 HFRC_DIV256 = 0x3 - Clock source is HFRC / 256 HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated).
PAGE 619
Apollo3 Blue Datasheet Table 884: CTRL4 Register Bits Bit Name Reset RW Description Counter/Timer A4 Interrupt Enable bit based on COMPR0. 9 TMRA4IE0 0x0 RW DIS = 0x0 - Disable counter/timer A4 from generating an interrupt based on COMPR0. EN = 0x1 - Enable counter/timer A4 to generate an interrupt based on COMPR0. Counter/Timer A4 Function Select. 8:6 TMRA4FN 0x0 RW SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A4, stop.
PAGE 620
Apollo3 Blue Datasheet Table 884: CTRL4 Register Bits Bit Name Reset RW Description Counter/Timer A4 Enable bit. 0 TMRA4EN 0x0 RW DIS = 0x0 - Counter/Timer A4 Disable. EN = 0x1 - Counter/Timer A4 Enable. 13.21.2.33CMPRAUXA4 Register Counter/Timer A4 Compare Registers OFFSET: 0x00000094 INSTANCE 0 ADDRESS: 0x40008094 Enhanced compare limits for timer half A.
PAGE 621
Apollo3 Blue Datasheet Table 888: CMPRAUXB4 Register Bits Bit Name Reset RW Description 31:16 CMPR3B4 0x0 RW Counter/Timer B4 Compare Register 3. Holds the upper limit for timer half B. 15:0 CMPR2B4 0x0 RW Counter/Timer B4 Compare Register 2. Holds the lower limit for timer half B. 13.21.2.35AUX4 Register Counter/Timer Auxiliary OFFSET: 0x0000009C INSTANCE 0 ADDRESS: 0x4000809C Control bit fields for both halves of timer 4.
PAGE 622
Apollo3 Blue Datasheet Table 890: AUX4 Register Bits Bit Name 27 TMRB4NOSYNC Reset RW Description Source clock synchronization control. 0x0 RW DIS = 0x0 - Synchronization on source clock NOSYNC = 0x1 - No synchronization on source clock Counter/Timer B4 Trigger Select. 26:23 TMRB4TRIG 0x0 RW 22 RSVD 0x0 RO 21:16 TMRB4LMT 0x0 RW 15 RSVD 0x0 RO DIS = 0x0 - Trigger source is disabled. A4OUT = 0x1 - Trigger source is CTIMERA4 OUT. B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.
PAGE 623
Apollo3 Blue Datasheet Table 890: AUX4 Register Bits Bit Name Reset RW Description Counter/Timer A4 Upper output polarity 13 TMRA4POL23 0x0 RW NORM = 0x0 - Upper output normal polarity INV = 0x1 - Upper output inverted polarity. Counter/Timer A4 Invert on trigger. 12 TMRA4TINV 11 TMRA4NOSYNC 0x0 RW DIS = 0x0 - Disable invert on trigger EN = 0x1 - Enable invert on trigger Source clock synchronization control.
PAGE 624
Apollo3 Blue Datasheet Table 892: TMR5 Register Bits Bit Name Reset RW 31:16 CTTMRB5 0x0 RO 15:0 CTTMRA5 0x0 RO Description Counter/Timer B5. Counter/Timer A5. 13.21.2.37CMPRA5 Register Counter/Timer A5 Compare Registers OFFSET: 0x000000A4 INSTANCE 0 ADDRESS: 0x400080A4 This register holds the compare limits for timer half A.
PAGE 625
Apollo3 Blue Datasheet Table 896: CMPRB5 Register Bits Bit Name Reset RW 31:16 CMPR1B5 0x0 RW 15:0 CMPR0B5 0x0 RW Description Counter/Timer B5 Compare Register 1. Counter/Timer B5 Compare Register 0. 13.21.2.39CTRL5 Register Counter/Timer Control OFFSET: 0x000000AC INSTANCE 0 ADDRESS: 0x400080AC Control bit fields for both halves of timer 0.
PAGE 626
Apollo3 Blue Datasheet Table 898: CTRL5 Register Bits Bit Name Reset RW Description Counter/Timer B5 Interrupt Enable bit for COMPR1. 26 TMRB5IE1 0x0 RW DIS = 0x0 - Disable counter/timer B5 from generating an interrupt based on COMPR1. EN = 0x1 - Enable counter/timer B5 to generate an interrupt based on COMPR1. Counter/Timer B5 Interrupt Enable bit for COMPR0. 25 TMRB5IE0 0x0 RW DIS = 0x0 - Disable counter/timer B5 from generating an interrupt based on COMPR0.
PAGE 627
Apollo3 Blue Datasheet Table 898: CTRL5 Register Bits Bit Name Reset RW Description Counter/Timer B5 Clock Select. 21:17 TMRB5CLK 0x0 RW TMRPIN = 0x0 - Clock source is TMRPINB. HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4 HFRC_DIV16 = 0x2 - Clock source is HFRC / 16 HFRC_DIV256 = 0x3 - Clock source is HFRC / 256 HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated).
PAGE 628
Apollo3 Blue Datasheet Table 898: CTRL5 Register Bits Bit Name Reset RW Description Counter/Timer A5 Interrupt Enable bit based on COMPR0. 9 TMRA5IE0 0x0 RW DIS = 0x0 - Disable counter/timer A5 from generating an interrupt based on COMPR0. EN = 0x1 - Enable counter/timer A5 to generate an interrupt based on COMPR0. Counter/Timer A5 Function Select. 8:6 TMRA5FN 0x0 RW SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A5, stop.
PAGE 629
Apollo3 Blue Datasheet Table 898: CTRL5 Register Bits Bit Name Reset RW Description Counter/Timer A5 Enable bit. 0 TMRA5EN 0x0 RW DIS = 0x0 - Counter/Timer A5 Disable. EN = 0x1 - Counter/Timer A5 Enable. 13.21.2.40CMPRAUXA5 Register Counter/Timer A5 Compare Registers OFFSET: 0x000000B4 INSTANCE 0 ADDRESS: 0x400080B4 Enhanced compare limits for timer half A.
PAGE 630
Apollo3 Blue Datasheet Table 902: CMPRAUXB5 Register Bits Bit Name Reset RW Description 31:16 CMPR3B5 0x0 RW Counter/Timer B5 Compare Register 3. Holds the upper limit for timer half B. 15:0 CMPR2B5 0x0 RW Counter/Timer B5 Compare Register 2. Holds the lower limit for timer half B. 13.21.2.42AUX5 Register Counter/Timer Auxiliary OFFSET: 0x000000BC INSTANCE 0 ADDRESS: 0x400080BC Control bit fields for both halves of timer 0.
PAGE 631
Apollo3 Blue Datasheet Table 904: AUX5 Register Bits Bit Name 27 TMRB5NOSYNC Reset RW Description Source clock synchronization control. 0x0 RW DIS = 0x0 - Synchronization on source clock NOSYNC = 0x1 - No synchronization on source clock Counter/Timer B5 Trigger Select. 26:23 TMRB5TRIG 0x0 RW 22 RSVD 0x0 RO 21:16 TMRB5LMT 0x0 RW 15 RSVD 0x0 RO DIS = 0x0 - Trigger source is disabled. A5OUT = 0x1 - Trigger source is CTIMERA5 OUT. B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.
PAGE 632
Apollo3 Blue Datasheet Table 904: AUX5 Register Bits Bit Name Reset RW Description Counter/Timer A5 Upper output polarity 13 TMRA5POL23 0x0 RW NORMAL = 0x0 - Upper output normal polarity INV = 0x1 - Upper output inverted polarity. Counter/Timer A5 Invert on trigger. 12 TMRA5TINV 11 TMRA5NOSYNC 0x0 RW DIS = 0x0 - Disable invert on trigger EN = 0x1 - Enable invert on trigger Source clock synchronization control.
PAGE 633
Apollo3 Blue Datasheet Table 906: TMR6 Register Bits Bit Name Reset RW 31:16 CTTMRB6 0x0 RO 15:0 CTTMRA6 0x0 RO Description Counter/Timer B6. Counter/Timer A6. 13.21.2.44CMPRA6 Register Counter/Timer A6 Compare Registers OFFSET: 0x000000C4 INSTANCE 0 ADDRESS: 0x400080C4 This register holds the compare limits for timer half A.
PAGE 634
Apollo3 Blue Datasheet Table 910: CMPRB6 Register Bits Bit Name Reset RW 31:16 CMPR1B6 0x0 RW 15:0 CMPR0B6 0x0 RW Description Counter/Timer B6 Compare Register 1. Counter/Timer B6 Compare Register 0. 13.21.2.46CTRL6 Register Counter/Timer Control OFFSET: 0x000000CC INSTANCE 0 ADDRESS: 0x400080CC This register holds the control bit fields for both halves of timer 6.
PAGE 635
Apollo3 Blue Datasheet Table 912: CTRL6 Register Bits Bit Name Reset RW Description Counter/Timer B6 Interrupt Enable bit for COMPR1. 26 TMRB6IE1 0x0 RW DIS = 0x0 - Disable counter/timer B6 from generating an interrupt based on COMPR1. EN = 0x1 - Enable counter/timer B6 to generate an interrupt based on COMPR1. Counter/Timer B6 Interrupt Enable bit for COMPR0. 25 TMRB6IE0 0x0 RW DIS = 0x0 - Disable counter/timer B6 from generating an interrupt based on COMPR0.
PAGE 636
Apollo3 Blue Datasheet Table 912: CTRL6 Register Bits Bit Name Reset RW Description Counter/Timer B6 Clock Select. 21:17 TMRB6CLK 0x0 RW TMRPIN = 0x0 - Clock source is TMRPINB. HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4 HFRC_DIV16 = 0x2 - Clock source is HFRC / 16 HFRC_DIV256 = 0x3 - Clock source is HFRC / 256 HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated).
PAGE 637
Apollo3 Blue Datasheet Table 912: CTRL6 Register Bits Bit Name Reset RW Description Counter/Timer A6 Interrupt Enable bit based on COMPR0. 9 TMRA6IE0 0x0 RW DIS = 0x0 - Disable counter/timer A6 from generating an interrupt based on COMPR0. EN = 0x1 - Enable counter/timer A6 to generate an interrupt based on COMPR0. Counter/Timer A6 Function Select. 8:6 TMRA6FN 0x0 RW SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A6, stop.
PAGE 638
Apollo3 Blue Datasheet Table 912: CTRL6 Register Bits Bit Name Reset RW Description Counter/Timer A6 Enable bit. 0 TMRA6EN 0x0 RW DIS = 0x0 - Counter/Timer A6 Disable. EN = 0x1 - Counter/Timer A6 Enable. 13.21.2.47CMPRAUXA6 Register Counter/Timer A6 Compare Registers OFFSET: 0x000000D4 INSTANCE 0 ADDRESS: 0x400080D4 Enhanced compare limits for timer half A.
PAGE 639
Apollo3 Blue Datasheet Table 916: CMPRAUXB6 Register Bits Bit Name Reset RW Description 31:16 CMPR3B6 0x0 RW Counter/Timer B6 Compare Register 3. Holds the upper limit for timer half B. 15:0 CMPR2B6 0x0 RW Counter/Timer B6 Compare Register 2. Holds the lower limit for timer half B. 13.21.2.49AUX6 Register Counter/Timer Auxiliary OFFSET: 0x000000DC INSTANCE 0 ADDRESS: 0x400080DC Control bit fields for both halves of timer 0.
PAGE 640
Apollo3 Blue Datasheet Table 918: AUX6 Register Bits Bit Name 27 TMRB6NOSYNC Reset RW Description Source clock synchronization control. 0x0 RW DIS = 0x0 - Synchronization on source clock NOSYNC = 0x1 - No synchronization on source clock Counter/Timer B6 Trigger Select. 26:23 TMRB6TRIG 0x0 RW 22 RSVD 0x0 RO 21:16 TMRB6LMT 0x0 RW 15 RSVD 0x0 RO DIS = 0x0 - Trigger source is disabled. A6OUT = 0x1 - Trigger source is CTIMERA6 OUT. B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.
PAGE 641
Apollo3 Blue Datasheet Table 918: AUX6 Register Bits Bit Name Reset RW Description Counter/Timer A6 Trigger Select. 10:7 TMRA6TRIG 0x0 RW 6:0 TMRA6LMT 0x0 RW DIS = 0x0 - Trigger source is disabled. B6OUT = 0x1 - Trigger source is CTIMERB6 OUT. B3OUT = 0x2 - Trigger source is CTIMERB3 OUT. A3OUT = 0x3 - Trigger source is CTIMERA3 OUT. A5OUT = 0x4 - Trigger source is CTIMERA5 OUT. B5OUT = 0x5 - Trigger source is CTIMERB5 OUT. A1OUT = 0x6 - Trigger source is CTIMERA1 OUT.
PAGE 642
Apollo3 Blue Datasheet This register holds the compare limits for timer half A. Table 921: CMPRA7 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 CMPR1A7 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMPR0A7 Table 922: CMPRA7 Register Bits Bit Name Reset RW 31:16 CMPR1A7 0x0 RW 15:0 CMPR0A7 0x0 RW Description Counter/Timer A7 Compare Register 1. Counter/Timer A7 Compare Register 0.
PAGE 643
Apollo3 Blue Datasheet 2 0 1 9 1 8 1 7 TMRB7CLK 1 6 1 5 1 4 RSVD 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 TMRA7CLK 0 1 0 0 TMRA7EN 2 1 TMRA7FN 2 2 TMRA7IE0 2 3 TMRA7IE1 TMRB7IE0 2 4 TMRA7CLR 2 5 TMRA7POL 2 6 TMRB7EN 2 7 TMRB7FN 2 8 TMRB7IE1 RSVD 2 9 TMRB7CLR 3 0 CTLINK7 3 1 TMRB7POL Table 925: CTRL7 Register Table 926: CTRL7 Register Bits Bit Name Reset RW Description Counter/Timer A7/B7 Link bit.
PAGE 644
Apollo3 Blue Datasheet Table 926: CTRL7 Register Bits Bit Name Reset RW Description Counter/Timer B7 Function Select. 24:22 TMRB7FN 0x0 RW SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B7, stop. REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B7, restart. PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B7, assert, count to CMPR1B7, deassert, stop. PULSE_CONT = 0x3 - Pulse continously.
PAGE 645
Apollo3 Blue Datasheet Table 926: CTRL7 Register Bits Bit Name Reset RW Description Counter/Timer A7 output polarity. 12 TMRA7POL 0x0 RW NORMAL = 0x0 - The polarity of the TMRPINA7 pin is the same as the timer output. INVERTED = 0x1 - The polarity of the TMRPINA7 pin is the inverse of the timer output. Counter/Timer A7 Clear bit. 11 TMRA7CLR 0x0 RW RUN = 0x0 - Allow counter/timer A7 to run CLEAR = 0x1 - Holds counter/timer A7 at 0x0000. Counter/Timer A7 Interrupt Enable bit based on COMPR1.
PAGE 646
Apollo3 Blue Datasheet Table 926: CTRL7 Register Bits Bit Name Reset RW Description Counter/Timer A7 Clock Select. 5:1 TMRA7CLK 0x0 RW TMRPIN = 0x0 - Clock source is TMRPINA. HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4 HFRC_DIV16 = 0x2 - Clock source is HFRC / 16 HFRC_DIV256 = 0x3 - Clock source is HFRC / 256 HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated).
PAGE 647
Apollo3 Blue Datasheet Table 928: CMPRAUXA7 Register Bits Bit Name Reset RW Description 31:16 CMPR3A7 0x0 RW Counter/Timer A7 Compare Register 3. Holds the upper limit for timer half A. 15:0 CMPR2A7 0x0 RW Counter/Timer A7 Compare Register 2. Holds the lower limit for timer half A. 13.21.2.55CMPRAUXB7 Register Counter/Timer B7 Compare Registers OFFSET: 0x000000F8 INSTANCE 0 ADDRESS: 0x400080F8 Enhanced compare limits for timer half B.
PAGE 648
Apollo3 Blue Datasheet 2 1 2 0 1 9 1 8 1 7 TMRB7LMT 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 TMRA7TRIG 2 2 TMRA7NOSYNC 2 3 TMRA7TINV 2 4 TMRA7POL23 2 5 TMRA7EN23 2 6 RSVD TMRB7POL23 2 7 RSVD RSVD 2 8 TMRB7TRIG 2 9 TMRB7TINV 3 0 TMRB7NOSYNC 3 1 TMRB7EN23 Table 931: AUX7 Register 0 4 0 3 0 2 0 1 0 0 TMRA7LMT Table 932: AUX7 Register Bits Bit Name Reset RW 31 RSVD 0x0 RO Description RESERVED Counter/Timer B7 Upper compare enable.
PAGE 649
Apollo3 Blue Datasheet Table 932: AUX7 Register Bits Bit Name Reset RW 21:16 TMRB7LMT 0x0 RW 15 RSVD 0x0 RO Description Counter/Timer B7 Pattern Limit Count. RESERVED Counter/Timer A7 Upper compare enable. 14 TMRA7EN23 0x0 RW DIS = 0x1 - Disable enhanced functions. EN = 0x0 - Enable enhanced functions. Counter/Timer A7 Upper output polarity 13 TMRA7POL23 0x0 RW NORM = 0x0 - Upper output normal polarity INV = 0x1 - Upper output inverted polarity. Counter/Timer A7 Invert on trigger.
PAGE 650
Apollo3 Blue Datasheet 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ENA0 1 7 ENB0 RSVD 1 8 ENA1 1 9 ENB1 2 0 ENA2 2 1 ENB2 2 2 ENA3 2 3 ENB3 2 4 ENA4 2 5 ENB4 2 6 ENA5 2 7 ENB5 2 8 ENA6 2 9 ENB6 3 0 ENA7 3 1 ENB7 Table 933: GLOBEN Register Table 934: GLOBEN Register Bits Bit Name Reset RW 31:16 RSVD 0x0 RO Description RESERVED Alternate enable for B7. 15 ENB7 0x1 RW 14 ENA7 0x1 RW LCO = 0x1 - Use local enable.
PAGE 651
Apollo3 Blue Datasheet Table 934: GLOBEN Register Bits Bit Name Reset RW Description Alternate enable for A3 6 ENA3 0x1 RW LCO = 0x1 - Use local enable. DIS = 0x0 - Disable CTIMER. Alternate enable for B2 5 ENB2 0x1 RW LCO = 0x1 - Use local enable. DIS = 0x0 - Disable CTIMER. Alternate enable for A2 4 ENA2 0x1 RW LCO = 0x1 - Use local enable. DIS = 0x0 - Disable CTIMER. Alternate enable for B1 3 ENB1 0x1 RW LCO = 0x1 - Use local enable. DIS = 0x0 - Disable CTIMER.
PAGE 652
Apollo3 Blue Datasheet Table 936: OUTCFG0 Register Bits Bit Name Reset RW 31 RSVD 0x0 RO Description RESERVED Pad output 9 configuration 30:28 CFG9 0x2 RW A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B0OUT = 0x5 - Output is B0OUT. A4OUT = 0x4 - Output is A4OUT. A2OUT = 0x3 - Output is A2OUT. A2OUT2 = 0x2 - Output is A2OUT2 ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 Pad output 8 configuration 27:25 CFG8 0x2 RW A7OUT2 = 0x7 - Output is A7OUT2.
PAGE 653
Apollo3 Blue Datasheet Table 936: OUTCFG0 Register Bits Bit Name Reset RW Description Pad output 4 configuration 14:12 CFG4 0x2 RW A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B5OUT = 0x5 - Output is B5OUT. A5OUT2 = 0x4 - Output is A5OUT2. A2OUT2 = 0x3 - Output is A2OUT2. A1OUT = 0x2 - Output is A1OUT ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 Pad output 3 configuration 11:9 CFG3 0x1 RW A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2.
PAGE 654
Apollo3 Blue Datasheet Pad output configuration 1. Table 937: OUTCFG1 Register 2 9 2 8 CFG19 2 7 2 6 2 5 CFG18 2 4 2 3 2 2 CFG17 2 1 2 0 1 9 CFG16 1 8 1 7 1 6 CFG15 1 5 RSVD 3 0 RSVD 3 1 1 4 1 3 1 2 CFG14 1 1 1 0 0 9 CFG13 0 8 0 7 0 6 CFG12 0 5 0 4 0 3 CFG11 0 2 0 1 0 0 CFG10 Table 938: OUTCFG1 Register Bits Bit Name Reset RW 31 RSVD 0x0 RO Description RESERVED Pad output 19 configuration 30:28 CFG19 0x2 RW A7OUT2 = 0x7 - Output is A7OUT2.
PAGE 655
Apollo3 Blue Datasheet Table 938: OUTCFG1 Register Bits Bit Name Reset RW Description Pad output 15 configuration 18:16 CFG15 0x2 RW 15 RSVD 0x0 RO A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. A4OUT2 = 0x5 - Output is A4OUT2. A7OUT = 0x4 - Output is A7OUT. B3OUT = 0x3 - Output is B3OUT. B3OUT2 = 0x2 - Output is B3OUT2 ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 RESERVED Pad output 14 configuration 14:12 CFG14 0x2 RW A7OUT2 = 0x7 - Output is A7OUT2.
PAGE 656
Apollo3 Blue Datasheet Table 938: OUTCFG1 Register Bits Bit Name Reset RW Description Pad output 10 configuration 2:0 CFG10 0x2 RW A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. A6OUT = 0x5 - Output is A6OUT. B4OUT2 = 0x4 - Output is B4OUT2. B3OUT2 = 0x3 - Output is B3OUT2. B2OUT = 0x2 - Output is B2OUT ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 13.21.2.
PAGE 657
Apollo3 Blue Datasheet Table 940: OUTCFG2 Register Bits Bit Name Reset RW Description Pad output 28 configuration 27:25 CFG28 0x2 RW A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B0OUT2 = 0x5 - Output is B0OUT2. A5OUT2 = 0x4 - Output is A5OUT2. A3OUT = 0x3 - Output is A3OUT. A7OUT = 0x2 - Output is A7OUT ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 Pad output 27 configuration 24:22 CFG27 0x2 RW A7OUT2 = 0x7 - Output is A7OUT2.
PAGE 658
Apollo3 Blue Datasheet Table 940: OUTCFG2 Register Bits Bit Name Reset RW Description Pad output 23 configuration 11:9 CFG23 0x1 RW A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B0OUT2 = 0x5 - Output is B0OUT2. A5OUT = 0x4 - Output is A5OUT. A7OUT = 0x3 - Output is A7OUT. B5OUT2 = 0x2 - Output is B5OUT2 ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 Pad output 22 configuration 8:6 CFG22 0x2 RW A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2.
PAGE 659
Apollo3 Blue Datasheet Table 941: OUTCFG3 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 RSVD 0 5 0 4 0 3 CFG31 0 2 0 1 0 0 CFG30 Table 942: OUTCFG3 Register Bits Bit Name Reset RW 31:6 RSVD 0x0 RO Description RESERVED Pad output 31 configuration 5:3 CFG31 0x2 RW A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B3OUT2 = 0x5 - Output is B3OUT2. B7OUT = 0x4 - Output is B7OUT.
PAGE 660
Apollo3 Blue Datasheet Table 944: INCFG Register Bits Bit Name Reset RW 31:16 RSVD 0x0 RO Description RESERVED CTIMER B7 input configuration 15 CFGB7 0x0 RW CT31 = 0x1 - Input is CT31 CT30 = 0x0 - Input is CT30 CTIMER A7 input configuration 14 CFGA7 0x0 RW CT29 = 0x1 - Input is CT29 CT28 = 0x0 - Input is CT28 CTIMER B6 input configuration 13 CFGB6 0x0 RW CT27 = 0x1 - Input is CT27 CT26 = 0x0 - Input is CT26 CTIMER A6 input configuration 12 CFGA6 0x0 RW CT25 = 0x1 - Input is CT25
PAGE 661
Apollo3 Blue Datasheet Table 944: INCFG Register Bits Bit Name Reset RW Description CTIMER B1 input configuration 3 CFGB1 0x0 RW CT7 = 0x1 - Input is CT7 CT6 = 0x0 - Input is CT6 CTIMER A1 input configuration 2 CFGA1 0x0 RW CT5 = 0x1 - Input is CT5 CT4 = 0x0 - Input is CT4 CTIMER B0 input configuration 1 CFGB0 0x0 RW CT3 = 0x1 - Input is CT3 CT2 = 0x0 - Input is CT2 CTIMER A0 input configuration 0 CFGA0 0x0 RW CT1 = 0x1 - Input is CT1 CT0 = 0x0 - Input is CT0 13.21.2.
PAGE 662
Apollo3 Blue Datasheet Table 946: INTEN Register Bits Bit Name Reset RW 27 CTMRB5C1INT 0x0 RW 26 CTMRA5C1INT 0x0 RW 25 CTMRB4C1INT 0x0 RW 24 CTMRA4C1INT 0x0 RW 23 CTMRB3C1INT 0x0 RW 22 CTMRA3C1INT 0x0 RW 21 CTMRB2C1INT 0x0 RW 20 CTMRA2C1INT 0x0 RW 19 CTMRB1C1INT 0x0 RW 18 CTMRA1C1INT 0x0 RW 17 CTMRB0C1INT 0x0 RW 16 CTMRA0C1INT 0x0 RW 15 CTMRB7C0INT 0x0 RW 14 CTMRA7C0INT 0x0 RW 13 CTMRB6C0INT 0x0 RW 12 CTMRA6C0INT 0x0 RW 11 CTMRB5C0INT 0x
PAGE 663
Apollo3 Blue Datasheet Table 946: INTEN Register Bits Bit Name Reset RW 4 CTMRA2C0INT 0x0 RW 3 CTMRB1C0INT 0x0 RW 2 CTMRA1C0INT 0x0 RW 1 CTMRB0C0INT 0x0 RW 0 CTMRA0C0INT 0x0 RW Description Counter/Timer A2 interrupt based on COMPR0. Counter/Timer B1 interrupt based on COMPR0. Counter/Timer A1 interrupt based on COMPR0. Counter/Timer B0 interrupt based on COMPR0. Counter/Timer A0 interrupt based on COMPR0. 13.21.2.
PAGE 664
Apollo3 Blue Datasheet Table 948: INTSTAT Register Bits Bit Name Reset RW 25 CTMRB4C1INT 0x0 RW 24 CTMRA4C1INT 0x0 RW 23 CTMRB3C1INT 0x0 RW 22 CTMRA3C1INT 0x0 RW 21 CTMRB2C1INT 0x0 RW 20 CTMRA2C1INT 0x0 RW 19 CTMRB1C1INT 0x0 RW 18 CTMRA1C1INT 0x0 RW 17 CTMRB0C1INT 0x0 RW 16 CTMRA0C1INT 0x0 RW 15 CTMRB7C0INT 0x0 RW 14 CTMRA7C0INT 0x0 RW 13 CTMRB6C0INT 0x0 RW 12 CTMRA6C0INT 0x0 RW 11 CTMRB5C0INT 0x0 RW 10 CTMRA5C0INT 0x0 RW 9 CTMRB4C0INT 0
PAGE 665
Apollo3 Blue Datasheet Table 948: INTSTAT Register Bits Bit Name Reset RW 2 CTMRA1C0INT 0x0 RW 1 CTMRB0C0INT 0x0 RW 0 CTMRA0C0INT 0x0 RW Description Counter/Timer A1 interrupt based on COMPR0. Counter/Timer B0 interrupt based on COMPR0. Counter/Timer A0 interrupt based on COMPR0. 13.21.2.65INTCLR Register Counter/Timer Interrupts: Clear OFFSET: 0x00000208 INSTANCE 0 ADDRESS: 0x40008208 Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
PAGE 666
Apollo3 Blue Datasheet Table 950: INTCLR Register Bits Bit Name Reset RW 23 CTMRB3C1INT 0x0 RW 22 CTMRA3C1INT 0x0 RW 21 CTMRB2C1INT 0x0 RW 20 CTMRA2C1INT 0x0 RW 19 CTMRB1C1INT 0x0 RW 18 CTMRA1C1INT 0x0 RW 17 CTMRB0C1INT 0x0 RW 16 CTMRA0C1INT 0x0 RW 15 CTMRB7C0INT 0x0 RW 14 CTMRA7C0INT 0x0 RW 13 CTMRB6C0INT 0x0 RW 12 CTMRA6C0INT 0x0 RW 11 CTMRB5C0INT 0x0 RW 10 CTMRA5C0INT 0x0 RW 9 CTMRB4C0INT 0x0 RW 8 CTMRA4C0INT 0x0 RW 7 CTMRB3C0INT 0x0
PAGE 667
Apollo3 Blue Datasheet Table 950: INTCLR Register Bits Bit Name Reset RW 0 CTMRA0C0INT 0x0 RW Description Counter/Timer A0 interrupt based on COMPR0. 13.21.2.66INTSET Register Counter/Timer Interrupts: Set OFFSET: 0x0000020C INSTANCE 0 ADDRESS: 0x4000820C Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
PAGE 668
Apollo3 Blue Datasheet Table 952: INTSET Register Bits Bit Name Reset RW 21 CTMRB2C1INT 0x0 RW 20 CTMRA2C1INT 0x0 RW 19 CTMRB1C1INT 0x0 RW 18 CTMRA1C1INT 0x0 RW 17 CTMRB0C1INT 0x0 RW 16 CTMRA0C1INT 0x0 RW 15 CTMRB7C0INT 0x0 RW 14 CTMRA7C0INT 0x0 RW 13 CTMRB6C0INT 0x0 RW 12 CTMRA6C0INT 0x0 RW 11 CTMRB5C0INT 0x0 RW 10 CTMRA5C0INT 0x0 RW 9 CTMRB4C0INT 0x0 RW 8 CTMRA4C0INT 0x0 RW 7 CTMRB3C0INT 0x0 RW 6 CTMRA3C0INT 0x0 RW 5 CTMRB2C0INT 0x0 R
PAGE 669
Apollo3 Blue Datasheet 14. System Timer Module 32-bit compare value ( x 8) = Comp IRQ 32-bit system timer CLK 32-bit capture registers ( x 4) GPIO Capture IRQ OVF IRQ Figure 84. Block Diagram for the System Timer 14.1 Functional Overview The Apollo3 Blue MCU System Timer (STIMER), shown above in Figure 84, tracks the global synchronized counter. It can be used for RTOS scheduling and real-time system tracking.
PAGE 670
Apollo3 Blue Datasheet The heart of the STIMER is a single 32-bit counter that keeps track of current time for the application running on the Apollo3 Blue MCU. This counter is reset at the actual power cycle reset of the MCU. It is generally never reset or changed again. Up to eight 32-bit comparator registers can be loaded each of which can generate an interrupt signal to the NVIC.
PAGE 671
Apollo3 Blue Datasheet 14.2.
PAGE 672
Apollo3 Blue Datasheet 14.2.2 STIMER Registers 14.2.2.1 STCFG Register Configuration Register OFFSET: 0x00000140 INSTANCE 0 ADDRESS: 0x40008140 The STIMER Configuration Register contains the software control for selecting the clock divider and source feeding the system timer.
PAGE 673
Apollo3 Blue Datasheet Table 955: STCFG Register Bits Bit 13 Name COMPARE_F_EN Reset 0x0 RW RW Description Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. DISABLE = 0x0 - Compare F disabled. ENABLE = 0x1 - Compare F enabled. 12 COMPARE_E_EN 0x0 RW Selects whether compare is enabled for the corresponding SCMPR register.
PAGE 674
Apollo3 Blue Datasheet 14.2.2.2 STTMR Register System Timer Count Register (Real Time Counter) OFFSET: 0x00000144 INSTANCE 0 ADDRESS: 0x40008144 The COUNTER Register contains the running count of time as maintained by incrementing for every rising clock edge of the clock source selected in the configuration register. It is this counter value that captured in the capture registers and it is this counter value that is compared against the various compare registers.
PAGE 675
Apollo3 Blue Datasheet Table 959: CAPTURECONTROL Register Bits Bit Name Reset RW 31:4 RSVD 0x0 RO Description RESERVED. Selects whether capture is enabled for the specified capture register. 3 CAPTURE3 0x0 RW DISABLE = 0x0 - Capture function disabled. ENABLE = 0x1 - Capture function enabled. Selects whether capture is enabled for the specified capture register. 2 CAPTURE2 0x0 RW DISABLE = 0x0 - Capture function disabled. ENABLE = 0x1 - Capture function enabled.
PAGE 676
Apollo3 Blue Datasheet 14.2.2.5 SCMPR1 Register Compare Register B OFFSET: 0x00000154 INSTANCE 0 ADDRESS: 0x40008154 The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE.
PAGE 677
Apollo3 Blue Datasheet Table 965: SCMPR2 Register Bits Bit Name 31:0 Reset SCMPR2 RW 0x0 RW Description Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_C_EN bit in the REG_CTIMER_STCGF register. 14.2.2.7 SCMPR3 Register Compare Register D OFFSET: 0x0000015C INSTANCE 0 ADDRESS: 0x4000815C The VALUE in this bit field is used to compare against the VALUE in the COUNTER register.
PAGE 678
Apollo3 Blue Datasheet Table 968: SCMPR4 Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 SCMPR4 Table 969: SCMPR4 Register Bits Bit Name 31:0 Reset SCMPR4 RW 0x0 RW Description Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_E_EN bit in the REG_CTIMER_STCGF register. 14.2.2.
PAGE 679
Apollo3 Blue Datasheet INSTANCE 0 ADDRESS: 0x40008168 The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt.
PAGE 680
Apollo3 Blue Datasheet Table 975: SCMPR7 Register Bits Bit Name 31:0 Reset SCMPR7 RW 0x0 RW Description Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_H_EN bit in the REG_CTIMER_STCGF register. 14.2.2.12SCAPT0 Register Capture Register A OFFSET: 0x000001E0 INSTANCE 0 ADDRESS: 0x400081E0 The STIMER capture Register A grabs the VALUE in the COUNTER register whenever capture condition (event) A is asserted.
PAGE 681
Apollo3 Blue Datasheet Table 979: SCAPT1 Register Bits Bit Name Reset RW Description 31:0 SCAPT1 0x0 RO Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set. 14.2.2.14SCAPT2 Register Capture Register C OFFSET: 0x000001E8 INSTANCE 0 ADDRESS: 0x400081E8 The STIMER capture Register C grabs the VALUE in the COUNTER register whenever capture condition (event) C is asserted.
PAGE 682
Apollo3 Blue Datasheet Table 983: SCAPT3 Register Bits Bit Name Reset RW Description 31:0 SCAPT3 0x0 RO Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set. 14.2.2.16SNVR0 Register System Timer NVRAM_A Register OFFSET: 0x000001F0 INSTANCE 0 ADDRESS: 0x400081F0 The NVRAM_A Register contains a portion of the stored epoch offset associated with the time in the COUNTER register.
PAGE 683
Apollo3 Blue Datasheet Table 987: SNVR1 Register Bits Bit Name Reset RW 31:0 SNVR1 0x0 RW Description Value of the 32-bit counter as it ticks over. 14.2.2.18SNVR2 Register System Timer NVRAM_C Register OFFSET: 0x000001F8 INSTANCE 0 ADDRESS: 0x400081F8 The NVRAM_C Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn.
PAGE 684
Apollo3 Blue Datasheet Table 991: SNVR3 Register Bits Bit Name Reset RW 31:0 SNVR3 0x0 RW Description Value of the 32-bit counter as it ticks over. 14.2.2.20STMINTEN Register STIMER Interrupt registers: Enable OFFSET: 0x00000300 INSTANCE 0 ADDRESS: 0x40008300 Set bits in this register to allow this module to generate the corresponding interrupt.
PAGE 685
Apollo3 Blue Datasheet Table 993: STMINTEN Register Bits Bit Name Reset RW Description COUNTER is greater than or equal to COMPARE register G. 6 COMPAREG 0x0 RW COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. COUNTER is greater than or equal to COMPARE register F. 5 COMPAREF 0x0 RW COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. COUNTER is greater than or equal to COMPARE register E.
PAGE 686
Apollo3 Blue Datasheet Table 995: STMINTSTAT Register Bits Bit Name Reset RW 31:13 RSVD 0x0 RO 12 CAPTURED 0x0 RW Description RESERVED. CAPTURE register D has grabbed the value in the counter CAPD_INT = 0x1 - Capture D interrupt status bit was set. CAPTURE register C has grabbed the value in the counter 11 CAPTUREC 0x0 RW CAPC_INT = 0x1 - CAPTURE C interrupt status bit was set.
PAGE 687
Apollo3 Blue Datasheet 14.2.2.22STMINTCLR Register STIMER Interrupt registers: Clear OFFSET: 0x00000308 INSTANCE 0 ADDRESS: 0x40008308 Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
PAGE 688
Apollo3 Blue Datasheet Table 997: STMINTCLR Register Bits Bit Name Reset RW Description COUNTER is greater than or equal to COMPARE register E. 4 COMPAREE 0x0 RW COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. COUNTER is greater than or equal to COMPARE register D. 3 COMPARED 0x0 RW COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. COUNTER is greater than or equal to COMPARE register C.
PAGE 689
Apollo3 Blue Datasheet Table 999: STMINTSET Register Bits Bit Name Reset RW 11 CAPTUREC 0x0 RW Description CAPTURE register C has grabbed the value in the counter CAPC_INT = 0x1 - CAPTURE C interrupt status bit was set. CAPTURE register B has grabbed the value in the counter 10 CAPTUREB 0x0 RW CAPB_INT = 0x1 - CAPTURE B interrupt status bit was set. CAPTURE register A has grabbed the value in the counter 9 CAPTUREA 0x0 RW CAPA_INT = 0x1 - CAPTURE A interrupt status bit was set.
PAGE 690
Apollo3 Blue Datasheet 15. Watchdog Timer Module CLR 128 Hz 16 Hz 1 Hz 1/16 Hz 8-bit Counter 8-bit Reset Value 8-bit Interrupt Value Compare Compare WDINT Control WDRES Figure 85. Block diagram for the Watchdog Timer Module 15.1 Functional Overview The Watchdog Timer (WDT), shown in Figure 85, is used to insure that software is operational, by resetting the Apollo3 Blue MCU if the WDT reaches a configurable value before being cleared by software.
PAGE 691
Apollo3 Blue Datasheet 15.2.1 Register Memory Map Table 1000: WDT Register Map Address(s) DS-A3-0p9p1 Register Name Description 0x40024000 CFG Configuration Register 0x40024004 RSTRT Restart the watchdog timer.
PAGE 692
Apollo3 Blue Datasheet 15.2.2 WDT Registers 15.2.2.1 CFG Register Configuration Register OFFSET: 0x00000000 INSTANCE 0 ADDRESS: 0x40024000 This is the configuration register for the watch dog timer. It controls the enable, interrupt set, clocks for the timer, the compare values for the counters to trigger a reset or interrupt. This register can only be written to if the watch dog timer is unlocked (WDTLOCK is not set).
PAGE 693
Apollo3 Blue Datasheet Table 1002: CFG Register Bits Bit Name Reset RW 0 WDTEN 0x0 RW Description This bitfield enables the WDT. 15.2.2.2 RSTRT Register Restart the watchdog timer. OFFSET: 0x00000004 INSTANCE 0 ADDRESS: 0x40024004 This register will Restart the watchdog timer. Writing a special key value into this register will result in the watch dog timer being reset, so that the count will start again.
PAGE 694
Apollo3 Blue Datasheet Table 1005: LOCK Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 RSVD 0 4 0 3 0 2 0 1 0 0 LOCK Table 1006: LOCK Register Bits Bit Name Reset RW 31:8 RSVD 0x0 RO Description This bitfield is reserved for future use. Writing 0x3A locks the watchdog timer. Once locked, the WDTCFG reg cannot be written and WDTEN is set.
PAGE 695
Apollo3 Blue Datasheet INSTANCE 0 ADDRESS: 0x40024200 Set bits in this register to allow this module to generate the corresponding interrupt.
PAGE 696
Apollo3 Blue Datasheet 15.2.2.7 INTCLR Register WDT Interrupt register: Clear OFFSET: 0x00000208 INSTANCE 0 ADDRESS: 0x40024208 Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
PAGE 697
Apollo3 Blue Datasheet Table 1016: INTSET Register Bits Bit Name Reset RW 31:1 RSVD 0x0 RO 0 WDTINT 0x0 RW DS-A3-0p9p1 Description This bitfield is reserved for future use. Watchdog Timer Interrupt. Page 697 of 909 2019 Ambiq Micro, Inc. All rights reserved.
PAGE 698
Apollo3 Blue Datasheet 16. Reset Generator Module RSTn PORn Power-on Detector Brown-out Detector Brown-out Detector 1.8 VBODn 2.1 VBODn VDDCORE Over-current Protection VDDMEM Over-current Protection VDDBLE Brown-out Detector OCPc SYSRESETn OCPf BODb SYSRESETREQn WDTRn Figure 86. Block diagram for the Reset Generator Module 16.1 Functional Overview The Reset Generator Module (RSTGEN) monitors a variety of reset signals and asserts the active low system reset (SYSRESETn) accordingly.
PAGE 699
Apollo3 Blue Datasheet RSTn Pad IO VDD RSTGEN RSTn RSTn Strong Pull Down brownout_n RST Button Figure 87. Block diagram of circuitry for Reset pin 16.3 Power-on Event An integrated power-on detector monitors the supply voltage and keeps SYSRESETn asserted while VDD is below the rising power-on voltage, VPOR+ (1.755 V). When VDD rises above VPOR at initial power on, the reset module will initialize the low power analog circuitry followed by de-assertion of SYSRESETn, and normal operation proceeds.
PAGE 700
Apollo3 Blue Datasheet 16.5 Software Reset A reset may be generated via software using the Application Interrupt and Reset Control Register (AIRCR) defined in the Cortex-M4. For additional information on the AIRCR, see the ARM document titled “CortexM4 Devices Generic User Guide.” The software reset request is not maskable.A second source for the identical software reset functionality is made available through the SWPOR register in the RSTGEN peripheral module. 16.
PAGE 701
Apollo3 Blue Datasheet 16.8.2 RSTGEN Registers 16.8.2.1 CFG Register Configuration Register OFFSET: 0x00000000 INSTANCE 0 ADDRESS: 0x40000000 Reset configuration register. This controls the reset enables for brownout condition, and for the expiration of the watch dog timer.
PAGE 702
Apollo3 Blue Datasheet Table 1021: SWPOI Register Bits Bit Name Reset RW 31:8 RSVD 0x0 RO Description RESERVED. 0x1B generates a software POI reset. This is a write-only register. Reading from this register will yield only all 0s. 7:0 SWPOIKEY 0x0 WO KEYVALUE = 0x1B - Writing 0x1B key value generates a software POI reset. 16.8.2.3 SWPOR Register Software POR Reset OFFSET: 0x00000008 INSTANCE 0 ADDRESS: 0x40000008 This is the software POR reset.
PAGE 703
Apollo3 Blue Datasheet Table 1024: TPIURST Register 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 TPIURST 3 1 RSVD Table 1025: TPIURST Register Bits Bit Name Reset RW 31:1 RSVD 0x0 RW 0 TPIURST 0x0 RW Description RESERVED. Static reset for the TPIU. Write to '1' to assert reset to TPIU. Write to '0' to clear the reset. 16.8.2.
PAGE 704
Apollo3 Blue Datasheet INSTANCE 0 ADDRESS: 0x40000204 Read bits from this register to discover the cause of a recent interrupt. Table 1028: INTSTAT Register 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BODH 3 1 RSVD Table 1029: INTSTAT Register Bits Bit Name Reset RW 31:1 RSVD 0x0 RO 0 BODH 0x0 RW Description RESERVED. Enables an interrupt that triggers when VCC is below BODH level.
PAGE 705
Apollo3 Blue Datasheet 16.8.2.8 INTSET Register Reset Interrupt register: Set OFFSET: 0x0000020C INSTANCE 0 ADDRESS: 0x4000020C Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
PAGE 706
Apollo3 Blue Datasheet Table 1035: STAT Register Bits Bit Name Reset RW 31 SBOOT 0x0 RW 30 FBOOT 0x0 RW 29:11 RSVD 0x0 RW 10 BOBSTAT 0x0 RW 9 BOFSTAT 0x0 RW 8 BOCSTAT 0x0 RW 7 BOUSTAT 0x0 RW 6 WDRSTAT 0x0 RW 5 DBGRSTAT 0x0 RW 4 POIRSTAT 0x0 RW 3 SWRSTAT 0x0 RW 2 BORSTAT 0x0 RW 1 PORSTAT 0x0 RW 0 EXRSTAT 0x0 RW DS-A3-0p9p1 Description Set when booting securely (SBL). Set if current boot was initiated by soft reset and resulted in Fast Boot (SBL).
PAGE 707
Apollo3 Blue Datasheet 17. UART Module Transmit FIFO APB APB Slave Transmit Interface UART TX Receive Interface UART RX Register Block Receive FIFO Interrupt Generation IRQ Figure 88. Block Diagram for the UART Module 17.
PAGE 708
Apollo3 Blue Datasheet Clocking to the UART serial logic is generated by a dedicated UARTCLK from the Clock Generator Module. The frequency of this clock is determined by the desired baud rate. For maximum baud rates, this clock would be clocked at the 24 MHz maximum as generated the HFRC. The major functional blocks of the UART are discussed briefly in the subsequent sections. 17.
PAGE 709
Apollo3 Blue Datasheet The UART Module supports independent CTS and RTS hardware flow control. All flow control configuration may be set using the UART_CR register. 17.5 Transmit FIFO and Receive FIFO The transmit and receive FIFOs may both be accessed via the same 8-bit word in the UART_DR register. The transmit FIFO stores up to 32 8-bit words and can be written using writes to UART_DR. The receive FIFO stores up to 32 12-bit words and can be read using reads to UART_DR.
PAGE 711
Apollo3 Blue Datasheet 17.6.2 UART Registers 17.6.2.
PAGE 712
Apollo3 Blue Datasheet INSTANCE 1 ADDRESS: 0x4001D004 UART Status Register 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 RSVD 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 FESTAT 2 9 PESTAT 3 0 BESTAT 3 1 OESTAT Table 1039: RSR Register Table 1040: RSR Register Bits Bit Name Reset RW 31:4 RSVD 0x0 RO Description This bitfield is reserved for future use. This is the overrun error indicator.
PAGE 713
Apollo3 Blue Datasheet 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 RSVD 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CTS 2 4 DSR 2 5 DCD 2 6 BUSY 2 7 RXFE 2 8 TXFF 2 9 RXFF 3 0 TXFE 3 1 TXBUSY Table 1041: FR Register Table 1042: FR Register Bits Bit Name Reset RW 31:9 RSVD 0x0 RO 8 TXBUSY 0x0 RO 7 TXFE 0x0 RO Description This bitfield is reserved for future use. This bit holds the transmit BUSY indicator.
PAGE 714
Apollo3 Blue Datasheet Table 1043: ILPR Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 RSVD 0 4 0 3 0 2 0 1 0 0 0 2 0 1 0 0 ILPDVSR Table 1044: ILPR Register Bits Bit Name Reset RW 31:8 RSVD 0x0 RO 7:0 ILPDVSR 0x0 RW Description This bitfield is reserved for future use. These bits hold the IrDA counter divisor. 17.6.2.
PAGE 715
Apollo3 Blue Datasheet Fractional Baud Rate Divisor Table 1047: FBRD Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 RSVD 0 3 0 2 0 1 0 0 DIVFRAC Table 1048: FBRD Register Bits Bit Name Reset RW 31:6 RSVD 0x0 RO 5:0 DIVFRAC 0x0 RW Description This bitfield is reserved for future use. These bits hold the baud fractional divisor. 17.6.2.
PAGE 716
Apollo3 Blue Datasheet Table 1050: LCRH Register Bits Bit Name Reset RW 4 FEN 0x0 RW 3 STP2 0x0 RW 2 EPS 0x0 RW 1 PEN 0x0 RW 0 BRK 0x0 RW Description This bit holds the FIFO enable. This bit holds the two stop bits select. This bit holds the even parity select. This bit holds the parity enable. This bit holds the break set. 17.6.2.
PAGE 717
Apollo3 Blue Datasheet Table 1052: CR Register Bits Bit Name Reset RW 10 DTR 0x0 RW 9 RXE 0x1 RW 8 TXE 0x1 RW 7 LBE 0x0 RW Description This bit enables data transmit ready. This bit is the receive enable. This bit is the transmit enable. This bit is the loopback enable. This bitfield is the UART clock select. 6:4 CLKSEL 0x0 RW 3 CLKEN 0x0 RW 2 SIRLP 0x0 RW 1 SIREN 0x0 RW 0 UARTEN 0x0 RW NOCLK = 0x0 - No UART clock. This is the low power default.
PAGE 718
Apollo3 Blue Datasheet Table 1054: IFLS Register Bits Bit Name Reset RW 31:6 RSVD 0x0 RO 5:3 RXIFLSEL 0x2 RW 2:0 TXIFLSEL 0x2 RW Description This bitfield is reserved for future use. These bits hold the receive FIFO interrupt level. These bits hold the transmit FIFO interrupt level. 17.6.2.
PAGE 719
Apollo3 Blue Datasheet Table 1056: IER Register Bits Bit Name Reset RW 4 RXIM 0x0 RW 3 DSRMIM 0x0 RW 2 DCDMIM 0x0 RW 1 CTSMIM 0x0 RW 0 TXCMPMIM 0x0 RW Description This bit holds the receive interrupt enable. This bit holds the modem DSR interrupt enable. This bit holds the modem DCD interrupt enable. This bit holds the modem CTS interrupt enable. This bit holds the modem TXCMP interrupt enable. 17.6.2.
PAGE 720
Apollo3 Blue Datasheet Table 1058: IES Register Bits Bit Name Reset RW 5 TXRIS 0x0 RO 4 RXRIS 0x0 RO 3 DSRMRIS 0x0 RO 2 DCDMRIS 0x0 RO 1 CTSMRIS 0x0 RO 0 TXCMPMRIS 0x0 RO Description This bit holds the transmit interrupt status. This bit holds the receive interrupt status. This bit holds the modem DSR interrupt status. This bit holds the modem DCD interrupt status. This bit holds the modem CTS interrupt status. This bit holds the modem TXCMP interrupt status. 17.6.2.
PAGE 721
Apollo3 Blue Datasheet Table 1060: MIS Register Bits Bit Name Reset RW 6 RTMIS 0x0 RO 5 TXMIS 0x0 RO 4 RXMIS 0x0 RO 3 DSRMMIS 0x0 RO 2 DCDMMIS 0x0 RO 1 CTSMMIS 0x0 RO 0 TXCMPMMIS 0x0 RO Description This bit holds the receive timeout interrupt status masked. This bit holds the transmit interrupt status masked. This bit holds the receive interrupt status masked. This bit holds the modem DSR interrupt status masked. This bit holds the modem DCD interrupt status masked.
PAGE 722
Apollo3 Blue Datasheet Table 1062: IEC Register Bits Bit Name Reset RW 7 FEIC 0x0 WO 6 RTIC 0x0 WO 5 TXIC 0x0 WO 4 RXIC 0x0 WO 3 DSRMIC 0x0 WO 2 DCDMIC 0x0 WO 1 CTSMIC 0x0 WO 0 TXCMPMIC 0x0 WO DS-A3-0p9p1 Description This bit holds the framing error interrupt clear. This bit holds the receive timeout interrupt clear. This bit holds the transmit interrupt clear. This bit holds the receive interrupt clear. This bit holds the modem DSR interrupt clear.
PAGE 723
Apollo3 Blue Datasheet 18. ADC and Temperature Sensor Module Figure 89. Block Diagram for ADC and Temperature Sensor SWT Calibration ADC_TT ADC_ET0 ADC_ET1 ADC_ET2 ADC_ET3 VCOMP TRIGINT Mode Controller ADC_I0 ADC_I1 ... ... ADC_I9 ADC_DIFF0 ADC_DIFF1 VSS VIN 14b ADC Temp Sensor Battery Resistor Divider ADC_REF VREFINT Bandgap Ref Digital Controller Window Comparator SLOT0 SLOT1 SLOT2 SLOT3 SLOT4 SLOT5 SLOT6 SLOT7 16 deep FIFO DMA HFRC Osc 18.
PAGE 724
Apollo3 Blue Datasheet ▪ Window comparator for monitoring voltages excursions into or out of user-selectable thresholds ▪ Up to 2.67 MS/s effective continuous, multi-slot sampling rate ▪ Interrupts for FIFO full, FIFO almost full, Scan Complete, Conversion Complete, Window Incursion Window Excursion 18.2 Functional Overview The Apollo3 Blue MCU integrates a sophisticated 14 bit successive approximation Analog to Digital Converter (ADC) block for sensing both internal and external voltages.
PAGE 725
Apollo3 Blue Datasheet 18.2.3 Triggering and Trigger Sources The ADC block can be initially triggered from one of six sources. Once triggered, it can be repetitively triggered from counter/timer number three (3). Four of the GPIO pins on the Apollo3 Blue MCU can be selected as trigger inputs to the ADC through a combination of settings in the PAD configuration registers in the GPIO block and settings in SLOT configuration registers described below.
PAGE 726
Apollo3 Blue Datasheet 3 0 2 9 2 8 Reserved 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 # Samples to Accum. 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 CHANNEL SELECT Reserved 0 5 0 4 Reserved 0 3 0 2 0 1 0 0 SLOT_ENABLE 3 1 WINDOW_COMP Table 1063: One SLOT Configuration Register The window comparator enable will be discussed in a subsequent section, below. See “DMA” on page 730. The number of samples to accumulate will also be explained in a subsequent section.
PAGE 727
Apollo3 Blue Datasheet and the FIFO will be written with the final average value. When each active slot obtains a sample from the ADC, it is added to the value in its accumulator. If a slot is set to accumulate 128 samples per result then the accumulator could reach a maximum value of: 128*(214-1) = 128*16383 = 2097024 = 221 - 128, hence the 21 bit accumulator.
PAGE 728
Apollo3 Blue Datasheet produce results at a different rate, the slot number generating the result is also written to the FIFO along with the total valid entry count within the FIFO. Table 1067: FIFO Register 3 1 3 0 2 9 2 8 R S V Slot Number.
PAGE 729
Apollo3 Blue Datasheet Table 1070: 10-bit FIFO Data Format # Samples 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 64 0 0 0 0 10 32 0 0 0 0 10 16 0 0 0 0 10 8 0 0 0 0 10 4 0 0 0 0 10 2 0 0 0 0 10 1 1 0 0 0 0 10 X X X X X X 9 8 7 6 5 4 3 2 1 0 6 5 4 3 2 X X X X X X X X X X X X X X X Table 1071: 8-bit FIFO Data Format # Samples 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 128 0 0 0 0 0 0 8.6 64 0 0 0 0 0 0 8.
PAGE 730
Apollo3 Blue Datasheet hardware populating the 8th valid FIFO entry, the FIFOOVR2 interrupt status bit will be set. In a FIFO full condition with 16 valid entries, the ADC will not overwrite existing valid FIFO contents. Before subsequent conversions will populate the FIFO with conversion data, software must free an open FIFO entry by writing to the FIFO Register or by resetting the ADC by disabling and enabling the ADC using the ADC_CFG register. 18.2.
PAGE 731
Apollo3 Blue Datasheet 18.2.9 Window Comparator A window comparator is provided which can generate an interrupt whenever a sample is determined to be inside the window limits or outside the window limits. These are two separate interrupts with separate interrupt enables. Thus one can request an interrupt any time a specified slot makes an excursion outside the window comparator limits.
PAGE 732
Apollo3 Blue Datasheet limits value to match the corresponding precision mode format for the enabled slots through the ADCSCWLIM register. 18.3 Operating Modes and the Mode Controller The mode controller of Figure 89 is a sophisticated state machine that manages not only the time slot conversions but also the power state of the ADC analog components and the hand shake with the clock generator to start the HFRC clock source if required.
PAGE 733
Apollo3 Blue Datasheet START SCAN Slot n = 0 SLOT n Enabled? N Y Y Initial Trigger? N Load Accumulate/ Divide Count (ADSEL(n) : 0 – 127) Sample Count(n) == ADSEL(n)? Y N Increment Sample Count(n) Sample, Accumulate, Initial Trigger = 0 Y Conversion Complete / Write FIFO, Initial Tigger = 1 Sample Count(n) == ADSEL(n)? N Increment n n == 7? SCAN DONE Figure 90. Scan Flowchart 18.3.1 Single Mode In single mode, one trigger event produces one scan of all enabled slots.
PAGE 734
Apollo3 Blue Datasheet 18.3.2 Repeat Mode Counter/Timer 3A has a bit in its configuration register that allows it to be a source of repetitive triggers for the ADC. If counter/timer 3 is initialized for this purpose then one only needs to turn on the RPTEN bit in the ADC configuration registers to enable this mode in the ADC. NOTE: the mode controller does not process these repetitive triggers from the counter/timer until a first triggering event occurs from the normal trigger sources.
PAGE 735
Apollo3 Blue Datasheet configuring the ADC slots and the ADC configuration register between conversion data collections, followed by disabling the ADC in the power control ADC enable register. Although this mode provides extremely low power operation, using the ADC in this mode will result in a cold start latency including reference buffer stabilization delay and a calibration sequence 100’s of microseconds, nominally. In this mode, the ADC must be reconfigured prior to any subsequent ADC operation. 18.
PAGE 736
Apollo3 Blue Datasheet ADC_I0 ... ... ADC_I9 ADC_DIFF0 ADC_DIFF1 VIN Temp Sensor ADC VSS VDD 10KΩ Input Voltage 5KΩ ≈ 1/3 Select Ch 0xD Ron≈ 500Ω BATTLOAD Figure 91. Switchable Battery Load The switchable load resistor is enabled by the BATTLOAD bit as shown in the ADCBATTLOAD Register of the MCUCTRL Registers. This feature is used to help estimate the health of the battery chemistry by estimating the internal resistance of the battery.
PAGE 737
Apollo3 Blue Datasheet Table 1075: ADC Register Map Address(s) Register Name Description 0x50010014 SL2CFG Slot 2 Configuration Register 0x50010018 SL3CFG Slot 3 Configuration Register 0x5001001C SL4CFG Slot 4 Configuration Register 0x50010020 SL5CFG Slot 5 Configuration Register 0x50010024 SL6CFG Slot 6 Configuration Register 0x50010028 SL7CFG Slot 7 Configuration Register 0x5001002C WULIM Window Comparator Upper Limits Register 0x50010030 WLLIM Window Comparator Lower Limits Reg
PAGE 738
Apollo3 Blue Datasheet 2 1 RSVD 2 0 1 9 1 8 1 7 1 6 1 5 1 4 RSVD 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 RSVD 0 4 0 3 0 2 0 1 0 0 RSVD 2 2 ADCEN 2 3 RPTEN RSVD 2 4 LPMODE 2 5 REFSEL 2 6 RSVD 2 7 DFIFORDEN 2 8 TRIGSEL 2 9 TRIGPOL 3 0 CLKSEL 3 1 CKMODE Table 1076: CFG Register Table 1077: CFG Register Bits Bit Name Reset RW 31:26 RSVD 0x0 RO Description RESERVED. Select the source and frequency for the ADC clock.
PAGE 739
Apollo3 Blue Datasheet Table 1077: CFG Register Bits Bit Name Reset RW Description Select the ADC reference voltage. 9:8 REFSEL 0x0 RW 7:5 RSVD 0x0 RO INT2P0 = 0x0 - Internal 2.0V Bandgap Reference Voltage INT1P5 = 0x1 - Internal 1.5V Bandgap Reference Voltage EXT2P0 = 0x2 - Off Chip 2.0V Reference EXT1P5 = 0x3 - Off Chip 1.5V Reference RESERVED. Clock mode register 4 CKMODE 0x0 RW LPCKMODE = 0x0 - Disable the clock between scans for LPMODE0. Set LPCKMODE to 0x1 while configuring the ADC.
PAGE 740
Apollo3 Blue Datasheet Table 1078: STAT Register 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 4 0 3 0 2 0 1 0 0 PWDSTAT 3 1 RSVD Table 1079: STAT Register Bits Bit Name Reset RW 31:1 RSVD 0x0 RO Description RESERVED. Indicates the power-status of the ADC. 0 PWDSTAT 0x0 RO ON = 0x0 - Powered on. POWERED_DOWN = 0x1 - ADC Low Power Mode 1.
PAGE 741
Apollo3 Blue Datasheet OFFSET: 0x0000000C INSTANCE 0 ADDRESS: 0x5001000C Slot 0 Configuration Register 2 8 2 7 2 6 2 5 2 4 2 3 2 2 RSVD 2 1 2 0 1 9 1 8 1 7 1 6 1 5 RSVD 1 4 1 3 RSVD 1 2 1 1 1 0 0 9 0 8 CHSEL0 0 7 0 6 0 5 0 4 RSVD 0 3 0 2 0 1 0 0 SLEN0 2 9 PRMODE0 3 0 ADSEL0 3 1 WCEN0 Table 1082: SL0CFG Register Table 1083: SL0CFG Register Bits Bit Name Reset RW 31:27 RSVD 0x0 RO Description RESERVED.
PAGE 742
Apollo3 Blue Datasheet Table 1083: SL0CFG Register Bits Bit Name Reset RW Description Select one of the 14 channel inputs for this slot. 11:8 CHSEL0 0x0 RW 7:2 RSVD 0x0 RO 1 WCEN0 0x0 RW SE0 = 0x0 - single ended external GPIO connection to pad16. SE1 = 0x1 - single ended external GPIO connection to pad29. SE2 = 0x2 - single ended external GPIO connection to pad11. SE3 = 0x3 - single ended external GPIO connection to pad31. SE4 = 0x4 - single ended external GPIO connection to pad32.
PAGE 743
Apollo3 Blue Datasheet Table 1085: SL1CFG Register Bits Bit Name Reset RW Description Select the number of measurements to average in the accumulate divide module for this slot. 26:24 ADSEL1 0x0 RW 23:18 RSVD 0x0 RO AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot. AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot. AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
PAGE 744
Apollo3 Blue Datasheet SL2CFG Register Slot 2 Configuration Register OFFSET: 0x00000014 INSTANCE 0 ADDRESS: 0x50010014 Slot 2 Configuration Register 2 8 2 7 2 6 2 5 2 4 2 3 2 2 RSVD 2 1 2 0 1 9 1 8 1 7 1 6 1 5 RSVD 1 4 1 3 RSVD 1 2 1 1 1 0 0 9 0 8 CHSEL2 0 7 0 6 0 5 0 4 RSVD 0 3 0 2 0 1 0 0 SLEN2 2 9 PRMODE2 3 0 ADSEL2 3 1 WCEN2 Table 1086: SL2CFG Register Table 1087: SL2CFG Register Bits Bit Name Reset RW 31:27 RSVD 0x0 RO Description RESERVED.
PAGE 745
Apollo3 Blue Datasheet Table 1087: SL2CFG Register Bits Bit Name Reset RW Description Select one of the 14 channel inputs for this slot. 11:8 CHSEL2 0x0 RW 7:2 RSVD 0x0 RO 1 WCEN2 0x0 RW SE0 = 0x0 - single ended external GPIO connection to pad16. SE1 = 0x1 - single ended external GPIO connection to pad29. SE2 = 0x2 - single ended external GPIO connection to pad11. SE3 = 0x3 - single ended external GPIO connection to pad31. SE4 = 0x4 - single ended external GPIO connection to pad32.
PAGE 746
Apollo3 Blue Datasheet Table 1089: SL3CFG Register Bits Bit Name Reset RW Description Select the number of measurements to average in the accumulate divide module for this slot. 26:24 ADSEL3 0x0 RW 23:18 RSVD 0x0 RO AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot. AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot. AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
PAGE 747
Apollo3 Blue Datasheet SL4CFG Register Slot 4 Configuration Register OFFSET: 0x0000001C INSTANCE 0 ADDRESS: 0x5001001C Slot 4 Configuration Register 2 8 2 7 2 6 2 5 2 4 2 3 2 2 RSVD 2 1 2 0 1 9 1 8 1 7 1 6 1 5 RSVD 1 4 1 3 RSVD 1 2 1 1 1 0 0 9 0 8 CHSEL4 0 7 0 6 0 5 0 4 RSVD 0 3 0 2 0 1 0 0 SLEN4 2 9 PRMODE4 3 0 ADSEL4 3 1 WCEN4 Table 1090: SL4CFG Register Table 1091: SL4CFG Register Bits Bit Name Reset RW 31:27 RSVD 0x0 RO Description RESERVED.
PAGE 748
Apollo3 Blue Datasheet Table 1091: SL4CFG Register Bits Bit Name Reset RW Description Select one of the 14 channel inputs for this slot. 11:8 CHSEL4 0x0 RW 7:2 RSVD 0x0 RO 1 WCEN4 0x0 RW SE0 = 0x0 - single ended external GPIO connection to pad16. SE1 = 0x1 - single ended external GPIO connection to pad29. SE2 = 0x2 - single ended external GPIO connection to pad11. SE3 = 0x3 - single ended external GPIO connection to pad31. SE4 = 0x4 - single ended external GPIO connection to pad32.
PAGE 749
Apollo3 Blue Datasheet Table 1093: SL5CFG Register Bits Bit Name Reset RW Description Select number of measurements to average in the accumulate divide module for this slot. 26:24 ADSEL5 0x0 RW 23:18 RSVD 0x0 RO AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot. AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot. AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
PAGE 750
Apollo3 Blue Datasheet SL6CFG Register Slot 6 Configuration Register OFFSET: 0x00000024 INSTANCE 0 ADDRESS: 0x50010024 Slot 6 Configuration Register 2 8 2 7 2 6 2 5 2 4 2 3 2 2 RSVD 2 1 2 0 1 9 1 8 1 7 1 6 1 5 RSVD 1 4 1 3 RSVD 1 2 1 1 1 0 0 9 0 8 CHSEL6 0 7 0 6 0 5 0 4 RSVD 0 3 0 2 0 1 0 0 SLEN6 2 9 PRMODE6 3 0 ADSEL6 3 1 WCEN6 Table 1094: SL6CFG Register Table 1095: SL6CFG Register Bits Bit Name Reset RW 31:27 RSVD 0x0 RO Description RESERVED.
PAGE 751
Apollo3 Blue Datasheet Table 1095: SL6CFG Register Bits Bit Name Reset RW Description Select one of the 14 channel inputs for this slot. 11:8 CHSEL6 0x0 RW 7:2 RSVD 0x0 RO 1 WCEN6 0x0 RW SE0 = 0x0 - single ended external GPIO connection to pad16. SE1 = 0x1 - single ended external GPIO connection to pad29. SE2 = 0x2 - single ended external GPIO connection to pad11. SE3 = 0x3 - single ended external GPIO connection to pad31. SE4 = 0x4 - single ended external GPIO connection to pad32.
PAGE 752
Apollo3 Blue Datasheet Table 1097: SL7CFG Register Bits Bit Name Reset RW Description Select the number of measurements to average in the accumulate divide module for this slot. 26:24 ADSEL7 0x0 RW 23:18 RSVD 0x0 RO AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot. AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot. AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
PAGE 753
Apollo3 Blue Datasheet WULIM Register Window Comparator Upper Limits Register OFFSET: 0x0000002C INSTANCE 0 ADDRESS: 0x5001002C Window Comparator Upper Limits Register Table 1098: WULIM Register 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 RSVD 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ULIM Table 1099: WULIM Register Bits Bit Name Reset RW 31:20 RSVD 0x0 RO 19:0 ULIM 0x0 RW Description
PAGE 754
Apollo3 Blue Datasheet FIFO Data and Valid Count Register OFFSET: 0x00000038 INSTANCE 0 ADDRESS: 0x50010038 The ADC FIFO Register contains the slot number and FIFO data for the oldest conversion data in the FIFO. The COUNT field indicates the total number of valid entries in the FIFO. A write to this register will pop one of the FIFO entries off the FIFO and decrease the COUNT by 1 if the COUNT is greater than zero.
PAGE 755
Apollo3 Blue Datasheet Table 1105: FIFOPR Register Bits Bit Name Reset RW 31 RSVDPR 0x0 RO 30:28 SLOTNUMPR 0x0 RO 27:20 COUNT 0x0 RO 19:0 DATA 0x0 RO Description RESERVED. Slot number associated with this FIFO data. Number of valid entries in the ADC FIFO. Oldest data in the FIFO. INTEN Register ADC Interrupt registers: Enable OFFSET: 0x00000200 INSTANCE 0 ADDRESS: 0x50010200 Set bits in this register to allow this module to generate the corresponding interrupt.
PAGE 756
Apollo3 Blue Datasheet Table 1107: INTEN Register Bits Bit Name Reset RW 3 FIFOOVR2 0x0 RW Description FIFO 100 percent full interrupt. FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt. FIFO 75 percent full interrupt. 2 FIFOOVR1 0x0 RW FIFO75INT = 0x1 - FIFO 75 percent full interrupt. ADC scan complete interrupt. 1 SCNCMP 0x0 RW SCNCMPINT = 0x1 - ADC scan complete interrupt. ADC conversion complete interrupt. 0 CNVCMP 0x0 RW CNVCMPINT = 0x1 - ADC conversion complete interrupt.
PAGE 757
Apollo3 Blue Datasheet Table 1109: INTSTAT Register Bits Bit Name Reset RW 3 FIFOOVR2 0x0 RW Description FIFO 100 percent full interrupt. FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt. FIFO 75 percent full interrupt. 2 FIFOOVR1 0x0 RW FIFO75INT = 0x1 - FIFO 75 percent full interrupt. ADC scan complete interrupt. 1 SCNCMP 0x0 RW SCNCMPINT = 0x1 - ADC scan complete interrupt. ADC conversion complete interrupt. 0 CNVCMP 0x0 RW CNVCMPINT = 0x1 - ADC conversion complete interrupt.
PAGE 758
Apollo3 Blue Datasheet Table 1111: INTCLR Register Bits Bit Name Reset RW 3 FIFOOVR2 0x0 RW Description FIFO 100 percent full interrupt. FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt. FIFO 75 percent full interrupt. 2 FIFOOVR1 0x0 RW FIFO75INT = 0x1 - FIFO 75 percent full interrupt. ADC scan complete interrupt. 1 SCNCMP 0x0 RW SCNCMPINT = 0x1 - ADC scan complete interrupt. ADC conversion complete interrupt. 0 CNVCMP 0x0 RW CNVCMPINT = 0x1 - ADC conversion complete interrupt.
PAGE 759
Apollo3 Blue Datasheet Table 1113: INTSET Register Bits Bit Name Reset RW 4 WCEXC 0x0 RW Description Window comparator voltage excursion interrupt. WCEXCINT = 0x1 - Window comparator voltage excursion interrupt. FIFO 100 percent full interrupt. 3 FIFOOVR2 0x0 RW FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt. FIFO 75 percent full interrupt. 2 FIFOOVR1 0x0 RW FIFO75INT = 0x1 - FIFO 75 percent full interrupt. ADC scan complete interrupt.
PAGE 760
Apollo3 Blue Datasheet INSTANCE 0 ADDRESS: 0x50010244 DMA Trigger Status Register Table 1116: DMATRIGSTAT Register 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 7 0 6 0 5 0 4 0 3 0 2 RSVD 0 1 0 0 D75STAT 2 8 DFULLSTAT 2 9 0 1 0 0 RSVD 3 0 DMAEN 3 1 Table 1117: DMATRIGSTAT Register Bits Bit Name Reset RW 31:2 RSVD 0x0 RO 1 DFULLSTAT 0x0 RO 0 D75STAT 0x0 RO Description RESERVED.
PAGE 761
Apollo3 Blue Datasheet Table 1119: DMACFG Register Bits Bit Name Reset RW 18 DPWROFF 0x0 RW Description Power Off the ADC System upon DMACPL. Mask the FIFOCNT and SLOTNUM when transferring FIFO contents to memory 17 DMAMSK 0x0 RW DIS = 0x0 - FIFO Contents are copied directly to memory without modification. EN = 0x1 - Only the FIFODATA contents are copied to memory on DMA transfers. The SLOTNUM and FIFOCNT contents are cleared to zero.
PAGE 762
Apollo3 Blue Datasheet Table 1121: DMABCOUNT Register Bits Bit Name Reset RW 31:0 RSVD 0x0 RO Description RESERVED.
PAGE 763
Apollo3 Blue Datasheet 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 UTARGADDR 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 DMATIP 3 0 DMACPL 3 1 DMAERR Table 1124: DMATARGADDR Register LTARGADDR Table 1125: DMATARGADDR Register Bits Bit Name Reset RW 31:19 UTARGADDR 0x400 RO 18:0 LTARGADDR 0x0 RW Description SRAM Target DMA Target Address DMASTAT Register DMA Status Register OFFSET: 0x000
PAGE 764
Apollo3 Blue Datasheet 19. Voltage Comparator Module PSEL[1:0] PWD VDDH VTEMP CMPIN0 POWER DOWN + CMPIN1 CMPOUT CMPRF0 CMPRF1 CMPRF2 _ LVLSEL[3:0] DAC NSEL[1:0] Figure 92. Block diagram for the Voltage Comparator Module 19.1 Functional Overview The Voltage Comparator Module, shown in Figure 92, measures a user-selectable voltage at all times. It provides interrupt and software access to the comparator output with multiple options for input and reference voltages.
PAGE 765
Apollo3 Blue Datasheet This is the detailed description of the Voltage Comparator Register Block. The Voltage Cmparator Register Block contains the software control for selecting the comparator inputs, powerdown control, observing comparator output status and enabling interrupts. 19.2.
PAGE 766
Apollo3 Blue Datasheet 19.2.2 VCOMP Registers 19.2.2.1 CFG Register Configuration Register OFFSET: 0x00000000 INSTANCE 0 ADDRESS: 0x4000C000 The Voltage Comparator Configuration Register contains the software control for selecting beween the 4 options for the positive input as well as the multiple options for the reference input.
PAGE 767
Apollo3 Blue Datasheet Table 1130: CFG Register Bits Bit Name Reset RW Description This bitfield selects the positive input to the comparator. 1:0 PSEL 0x0 RW VDDADJ = 0x0 - Use VDDADJ for the positive input. VTEMP = 0x1 - Use the temperature sensor output for the positive input. Note: If this channel is selected for PSEL, the bandap circuit required for temperature comparisons will automatically turn on. The bandgap circuit requires 11us to stabalize.
PAGE 768
Apollo3 Blue Datasheet Key Register for Powering Down the Voltage Comparator 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 OUTHI 3 1 OUTLOW Table 1133: PWDKEY Register PWDKEY Table 1134: PWDKEY Register Bits Bit Name Reset RW 31:0 PWDKEY 0x0 RW Description Key register value. Key = 0x37 - Key 19.2.2.
PAGE 769
Apollo3 Blue Datasheet INSTANCE 0 ADDRESS: 0x4000C204 Read bits from this register to discover the cause of a recent interrupt.
PAGE 770
Apollo3 Blue Datasheet Table 1140: INTCLR Register Bits Bit Name Reset RW 0 OUTLOW 0x0 RW Description This bit is the vcompout low interrupt. 19.2.2.7 INTSET Register Voltage Comparator Interrupt registers: Set OFFSET: 0x0000020C INSTANCE 0 ADDRESS: 0x4000C20C Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
PAGE 771
Apollo3 Blue Datasheet 20. Voltage Regulator Module To Core LDO To Logic SIMO Buck VDD To Memory LDO Buck To Comms LDO To Analog Blocks LDO Figure 93. Block Diagram for the Voltage Regulator Module 20.1 Functional Overview The Voltage Regulator Module down-converts and regulates the supply voltage, VDD, with extremely high efficiency. A pair of Buck Converters enables down-conversion from the power supply input (e.g., a battery) at efficiency of >80%.
PAGE 772
Apollo3 Blue Datasheet For cost/area constrained designs, the SIMO buck can be disabled and on-die LDO regulators can be used. In this configuration, the OTP CUSTOMER_TRIM setting must have the SIMO_BUCK_enable set to ‘0’. In this configuration, the SIMO buck will remained powered down. The SIMO buck cannot be dynamically enabled/disabled after initial device reset. There is also a zero length detect circuit to ensure the regulated voltages from the SIMO buck do not drop out. 20.
PAGE 773
Apollo3 Blue Datasheet Figure 94. BLE/Burst Buck Ton Adjustment Diagram 20.3.2 BLE/Burst Buck zero length detect In addition to the Ton adjustment, there is a zero length detect circuit to ensure the regulated voltage does not drop out. The zero length detect is a mechanism to detect the length of time the buck is indicating that the buck voltage is below a certain threshold.
PAGE 774
Apollo3 Blue Datasheet 21. Electrical Characteristics For all tables TA = -40ºC to 85ºC, Typical values at 25ºC, 1.8v, unless otherwise specified. IMPORTANT NOTICE Specifications and other information in this advanced version of the Apollo3 Blue MCU Datasheet should be regarded as preliminary and subject to change. 21.1 Absolute Maximum Ratings The absolute maximum ratings are the limits to which the device can be subjected without permanently damaging the device and are stress ratings only.
PAGE 775
Apollo3 Blue Datasheet Table 1143: Absolute Maximum Ratings VESDCDM (1) High (2) ESD Charged Device Model (CDM) 250 V side power switches are available on PAD3 and PAD36 A low side power switch is available on PAD37 and PAD41 DS-A3-0p9p1 Page 775 of 909 2019 Ambiq Micro, Inc. All rights reserved.
PAGE 776
Apollo3 Blue Datasheet 21.2 Recommended Operating Conditions Table 1144: Recommended Operating Conditionsa Symbol Parameter Min Typ Max Unit VDDP Pad supply voltage 1.755 3.63 V VDDH Digital supply voltage 1.755 3.63 V VDDA Analog supply voltage 1.755 3.63 V VDDB BLE/Burst Buck Converter supply voltage 1.755 3.63 V VCC RF supply voltage 1.755 3.
PAGE 777
Apollo3 Blue Datasheet Table 1145: Current Consumption ISDS2-384RET ISDS2-8RET ISDS3 System Deep Sleep mode 2 current w/ 384kB retention WFI instruction with SLEEPDEEP=1, XTAL ON, buck converters enabled in LP mode, all I/O power domains powered OFF, BLE OFF, 384kB SRAM in retention 3.3v 2.7 μA 1.8v 3.
PAGE 778
Apollo3 Blue Datasheet 21.
PAGE 779
Apollo3 Blue Datasheet 21.6 Bluetooth Low Energy (BLE) Parametera Symbol Test Conditions Min Typ Max Unit 1 Mbps BLE ideal transmitter, <=37 bytes, PER < 30.8% -92 -93 -94 dBm 0.5 dB 0 dBm AC Characteristics - Rx RSENS Receiver sensitivity RSENS, VAR Rx sensitivity variance between channels PRX, MAX Maximum receiver input power C/Ico-channel Co-channel interference PB FET -0.5 PER < 30.8% Wanted signal at – 67dBm, modulated interferer in channel, PER < 30.
PAGE 780
Apollo3 Blue Datasheet Symbol Parameter Test Conditions Min Typ Max Unit +VAD- VADCIN_DIFF Input voltage range in differential mode -VADCREF/ 2 CREF/2 V VADCINN VADCINP Absolute differential input voltage range 0 VDDH V VADCREF_15E External reference range (1.5v mode) voltage VADCREF_20E External reference range (2.0v mode) voltage VADCREF_15I 1.425 1.5 1.575 V 1.9 2.0 2.1 V Internal reference voltage range (1.5v mode) 1.475 1.5 1.
PAGE 781
Apollo3 Blue Datasheet Symbol Parameter Test Conditions Min Typ Max Unit TSNGLSLOT_SC NCMP_PM12 Delay from scan start to scan complete, precision mode 12 28 cycles TSNGLSLOT_SC NCMP_PM10 Delay from scan start to scan complete, precision mode 10 22 cycles TSNGLSLOT_SC NCMP_PM8 Delay from scan start to scan complete, precision mode 8 18 cycles TCAL Calibration Period 6415 cycles 10.9 ENOB DYNAMIC CHARACTERISTICS, External 2v Reference (LDO or Buck Mode,a Single/Diff.
PAGE 782
Apollo3 Blue Datasheet Symbol Parameter Test Conditions Min Typ Max Unit NMCADC No missing codes INLADC Integral nonlinearity Full input range +/- 2.4 +/- 3.5 LSB DNLADC Differential nonlinearity Full input range +/- 0.9 +/- 1.7 LSB EADC_OFFEST Offset error 1 %FS EADC_GAIN Gain error 1 %FS 14 bits 1 INTERNAL TEMPERATURE SENSOR ETEMP Temperature sensor accuracy STEMP Temperature sensor slope +/- 3 °C 3.
PAGE 783
Apollo3 Blue Datasheet 21.8 Buck Converter Table 1150: SIMO Buck Converter Symbol Parameter Test Conditions Min Typ Max Unit LSBUCK Buck converter inductance (VSIMO) 2.2 µH CBUCK Buck converter output capacitance (2) (VDDC, VDDF) 2.2 µF Internal Voltages MEM LDO MEMLP LDO VDDF_LP VDDF CORE LDO VDDP VDDC SIMO BUCK SIMOBUCK_SW LSBUCK SIMOBUCK _SWSEL VSSP VDDC VDDF CBUCK CBUCK Figure 95.
PAGE 784
Apollo3 Blue Datasheet Internal Voltages VDDBH VDCDCRF VDDB BLE BUCK VDDBH_SW LBLEBUCK VDDBH VDCDCRF VSSB 0 ohm* CBLEBUCK CDCDCRF *Replace with a ferrite bead to filter high-frequency noise Figure 96. External Components for BLE Buck DS-A3-0p9p1 Page 784 of 909 2019 Ambiq Micro, Inc. All rights reserved.
PAGE 785
Apollo3 Blue Datasheet 21.9 Power-On RESET (POR) and Brown-Out Detector (BOD) Table 1152: Power-On Reset (POR) and Brown-Out Detector (BOD) Symbol Parameter Min Typ Max Unit VPOR_RISING POR rising threshold voltage 1.62 1.755 V VBODL_FALLING Brownout detection low falling threshold voltage 1.62 1.755 V DS-A3-0p9p1 Page 785 of 909 2019 Ambiq Micro, Inc. All rights reserved.
PAGE 786
Apollo3 Blue Datasheet 21.
PAGE 787
Apollo3 Blue Datasheet 21.11Voltage Comparator (VCOMP) Table 1154: Voltage Comparator (VCOMP) Symbol Parameter Test Conditions Min Typ Max Unit VDDA V VCOMPIN Input voltage range VCOMPIN_OV Input offset voltage ICOMPIN_LEAK Input leakage current TCOMP_RTRIG Rising voltage trigger response time 38 µs TCOMP_FTRIG Falling voltage trigger response time 12 µs VHYST Hysteresis DS-A3-0p9p1 0 30 Page 787 of 909 TBD V 1 nA mV 2019 Ambiq Micro, Inc. All rights reserved.
PAGE 788
Apollo3 Blue Datasheet 21.12 Inter-Integrated Circuit (I2C) Interface Table 1155: Inter-Integrated Circuit (I2C) Interface Symbol Parameter VCC Min Typ Max Unit 1000 kHz fSCL SCL input clock frequency 1.7 V - 3.6 V 10 tLOW Low period of SCL clock 1.7 V - 3.6 V 1.3 µs tHIGH High period of SCL clock 1.7 V - 3.6 V 600 ns tRISE Rise time of SDA and SCL 1.7 V - 3.6 V 300 ns tFALL Fall time of SDA and SCL 1.7 V - 3.6 V 300 ns tHD:STA START condition hold time 1.7 V - 3.
PAGE 789
Apollo3 Blue Datasheet 21.
PAGE 790
Apollo3 Blue Datasheet 1/FSCLK SPOL = 0 TSCLK_F SCLK TSCLK_R SPOL = 1 TSCLK_LO TSCLK_HI TSCLK_LO TSCLK_HI TSU_MI THD_MI MISO THD_MO TVALID_MO MOSI Figure 99. SPI Master Mode, Phase = 1 DS-A3-0p9p1 Page 790 of 909 2019 Ambiq Micro, Inc. All rights reserved.
PAGE 791
Apollo3 Blue Datasheet 21.
PAGE 792
Apollo3 Blue Datasheet Figure 100. SPI Slave Mode, Phase = 0 CE TCE_LEAD TCE_LAG 1/FSCLK TSCLK_R SPOL = 0 SCLK SPOL = 1 TSCLK_LO TSCLK_HI TSCLK_F TSCLK_LO TSCLK_HI TSU_SI THD_SI MOSI THD_SO TCE_SDO TVALID_SO TCE_SDZ MISO Figure 101. SPI Slave Mode, Phase = 1 DS-A3-0p9p1 Page 792 of 909 2019 Ambiq Micro, Inc. All rights reserved.
PAGE 793
Apollo3 Blue Datasheet 21.15PDM Interface Table 1158: Pulse Density Modulation (PDM) Interface Symbol Parameter Min Typ Max Unit DCPDMCLK PDM clock duty cyclea 45 - 55 % DCPDMCLK_HI PDM high frequency clock duty cycleb 48 - 52 % TPDM_RISE PDM clock and data rise time - - TBD ns TPDM_FALL PDM clock and data fall time - - TBD ns TSU_PDM PDM input data setup time - - TBD ns THD_PDM PDM input data hold time TBD - - ns a. Applicable when FPDMCLK <= 2.
PAGE 794
Apollo3 Blue Datasheet 21.18Counter/Timer (CTIMER) Table 1161: Counter/Timer (CTIMER) Symbol Parameter FCTIMER Input frequency TCTIMER Capture pulse width Min Typ Max Unit - - 24 MHz - - 21.
PAGE 795
Apollo3 Blue Datasheet Table 1163: General Purpose Input/Output (GPIO) TRISE_STD Rise time - - TBD ns TFALL_STD Fall time - - TBD ns ISRC_STD Output source current, 2mA drive strength - 3.5 - mA ISNK_STD Output sink current, 2mA drive strength - 3.4 - mA ISRC_STD Output source current, 4mA drive strength - 7.1 - mA ISNK_STD Output sink current, 4mA drive strength - 6.8 - mA ISRC_STD Output source current, 8mA drive strength - 14.
PAGE 796
Apollo3 Blue Datasheet 21.
PAGE 797
Apollo3 Blue Datasheet 22. Package Mechanical Information 22.1 CSP Package Notes: 1. Dimension b is measured at the maximum solder bump diameter, parallel to primary datum C. 2. This pod is for device Apollo3 without backside coating. 3. eF is the distance between the center lines of row C and row D of balls. 4. eG is the vertical offset from center of package to center of D5 ball. 5. eH is the horizontal offset from center of package to center of D5 ball. 6.
PAGE 804
Apollo3 Blue Datasheet 23. Appendix 1. FLASH OTP 0 Customer Info Space (Info0) 23.1 Flash OTP INSTANCE0 INFO0 Words Customer OTP Block 0 of Instance 0. INSTANCE 0 BASE ADDRESS:0x00000000 This is the detailed description of the contents of the Customer OTP for Apollo3. DS-A3-0p9p1 Page 804 of 909 2019 Ambiq Micro, Inc. All rights reserved.
PAGE 805
Apollo3 Blue Datasheet 23.1.
PAGE 806
Apollo3 Blue Datasheet Table 1165: Flash OTP INSTANCE0 INFO0 Register Map Address(s) DS-A3-0p9p1 Register Name Description 0x00001810 CUSTKEKW4 Customer KEK Word4 0x00001814 CUSTKEKW5 Customer KEK Word5 0x00001818 CUSTKEKW6 Customer KEK Word6 0x0000181C CUSTKEKW7 Customer KEK Word7 0x00001820 CUSTKEKW8 Customer KEK Word0 0x00001824 CUSTKEKW9 Customer KEK Word9 0x00001828 CUSTKEKW10 Customer KEK Word10 0x0000182C CUSTKEKW11 Customer KEK Word11 0x00001830 CUSTKEKW12 Customer KEK
PAGE 807
Apollo3 Blue Datasheet Table 1165: Flash OTP INSTANCE0 INFO0 Register Map Address(s) DS-A3-0p9p1 Register Name Description 0x000018A8 CUSTAUTHW10 Customer AUTH Key Word10 0x000018AC CUSTAUTHW11 Customer AUTH Key Word11 0x000018B0 CUSTAUTHW12 Customer AUTH Key Word12 0x000018B4 CUSTAUTHW13 Customer AUTH Key Word13 0x000018B8 CUSTAUTHW14 Customer AUTH Key Word14 0x000018BC CUSTAUTHW15 Customer AUTH Key Word15 0x000018C0 CUSTAUTHW16 Customer AUTH Key Word16 0x000018C4 CUSTAUTHW17 Cu
PAGE 808
Apollo3 Blue Datasheet Table 1165: Flash OTP INSTANCE0 INFO0 Register Map Address(s) DS-A3-0p9p1 Register Name Description 0x00001940 CUSTPUBKEYW16 Customer Public Key Word16 0x00001944 CUSTPUBKEYW17 Customer Public Key Word17 0x00001948 CUSTPUBKEYW18 Customer Public Key Word18 0x0000194C CUSTPUBKEYW19 Customer Public Key Word19 0x00001950 CUSTPUBKEYW20 Customer Public Key Word20 0x00001954 CUSTPUBKEYW21 Customer Public Key Word21 0x00001958 CUSTPUBKEYW22 Customer Public Key Word22
PAGE 809
Apollo3 Blue Datasheet Table 1165: Flash OTP INSTANCE0 INFO0 Register Map Address(s) DS-A3-0p9p1 Register Name Description 0x000019D8 CUSTPUBKEYW54 Customer Public Key Word54 0x000019DC CUSTPUBKEYW55 Customer Public Key Word55 0x000019E0 CUSTPUBKEYW56 Customer Public Key Word56 0x000019E4 CUSTPUBKEYW57 Customer Public Key Word57 0x000019E8 CUSTPUBKEYW58 Customer Public Key Word58 0x000019EC CUSTPUBKEYW59 Customer Public Key Word59 0x000019F0 CUSTPUBKEYW60 Customer Public Key Word60
PAGE 810
Apollo3 Blue Datasheet 23.1.2 Flash OTP INSTANCE0 INFO0 Words 23.1.2.1 SIGNATURE0 Register INFO0 Signature OFFSET: 0x00000000 INSTANCE 0 ADDRESS: 0x00000000 Word 0 (low word, bits 31:0) of the 128-bit INFO0 signature.
PAGE 811
Apollo3 Blue Datasheet 23.1.2.3 SIGNATURE2 Register INFO0 Signature OFFSET: 0x00000008 INSTANCE 0 ADDRESS: 0x00000008 Word 2 (bits 95:64) of the 128-bit INFO0 signature.
PAGE 812
Apollo3 Blue Datasheet This 32-bit word contains the customer programmable security.
PAGE 813
Apollo3 Blue Datasheet Table 1175: SECURITY Register Bits Bit Name Reset RW Description Secure Debug Lock. Should be set to 0 for production parts. (used by bootloader SW) 10 SDBG 0x1 LOCK = 0x0 - Prevents debugger control while PROTLOCK is not set. UNLOCK = 0x1 - Debugger is allowed to connect during secure boot stage. Enable bootloader action at reset.
PAGE 814
Apollo3 Blue Datasheet Table 1177: CUSTOMERTRIM Register Bits Bit Name Reset RW 31:3 RSVD 0x3fffffff 2 BLE_FEATURE_enable 0x1 1 BLE_BUCK_enable 0x1 0 SIMO_BUCK_enable 0x1 Description Reserved BLE Feature Enable Bit BLE Buck Enable Bit SIMO Buck Enable Bit 23.1.2.7 CUSTOMERTRIM2 Register Customer trim values word2 OFFSET: 0x00000018 INSTANCE 0 ADDRESS: 0x00000018 Customer Programmable trim overrides. configuration.
PAGE 815
Apollo3 Blue Datasheet Table 1180: SECURITYOVR Register 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 POL 3 1 RSVD 0 3 0 2 0 1 0 0 GPIO Table 1181: SECURITYOVR Register Bits Bit Name Reset 31:8 RSVD 0xffffff RW Description Reserved GPIO polarity to indicate update.
PAGE 816
Apollo3 Blue Datasheet Table 1183: SECURITYWIREDCFG Register Bits Bit Name Reset RW Description Wired interface configuration 2:0 IFC 0x7 IFC_UART = 0x1 - UART interface IFC_SPI = 0x2 - SPI interface IFC_I2C = 0x4 - I2C interface 23.1.2.10SECURITYWIREDIFCCFG0 Register Security Wired Interface configuration word0 OFFSET: 0x00000028 INSTANCE 0 ADDRESS: 0x00000028 This 32-bit word contains the interface configuration word0 for the UART wired update.
PAGE 817
Apollo3 Blue Datasheet Table 1185: SECURITYWIREDIFCCFG0 Register Bits Bit Name Reset 0 UART 0x1 RW Description UART Module 23.1.2.11SECURITYWIREDIFCCFG1 Register Security Wired Interface configuration word1 OFFSET: 0x0000002C INSTANCE 0 ADDRESS: 0x0000002C This 32-bit word contains the interface configuration word1 for the UART wired update.
PAGE 818
Apollo3 Blue Datasheet Table 1189: SECURITYWIREDIFCCFG2 Register Bits Bit Name Reset 31:24 RSVD2 0xff 23:16 ALTPADCFG 0xff 15:12 RSVD1 0xf 11:8 GPIOCFG 0xf 7:0 PADCFG 0xff RW Description Reserved 8 bit value representing the raw ALTPADCFG bits for this pin Reserved 4 bit value representing the raw GPIOCFG bits for this pin 8 bit value representing the raw PADREG bits for this pin 23.1.2.
PAGE 819
Apollo3 Blue Datasheet INSTANCE 0 ADDRESS: 0x00000038 This 32-bit word contains the raw Pin configuration for the UART wired interface pin 2.
PAGE 820
Apollo3 Blue Datasheet Table 1195: SECURITYWIREDIFCCFG5 Register Bits Bit Name Reset 15:12 RSVD1 0xf 11:8 GPIOCFG 0xf 7:0 PADCFG 0xff RW Description Reserved 4 bit value representing the raw GPIOCFG bits for this pin 8 bit value representing the raw PADREG bits for this pin 23.1.2.
PAGE 821
Apollo3 Blue Datasheet Table 1199: SECURITYSRAMRESV Register Bits Bit Name Reset 31:0 SRAM_RESV 0xffffffff RW Description SRAM Reservation 23.1.2.18WRITEPROTECTL Register Flash write-protection bits. OFFSET: 0x000001F8 INSTANCE 0 ADDRESS: 0x000001F8 These bits write-protect flash in 16KB chunks.
PAGE 822
Apollo3 Blue Datasheet Table 1203: WRITEPROTECTH Register Bits Bit Name Reset 31:0 CHUNKS 0xffffffff RW Description Write protect flash 0x00080000 - 0x000FFFFF. Each bit provides write protection for 16KB chunks of flash data space. 23.1.2.20COPYPROTECTL Register Flash copy/read-protection bits. OFFSET: 0x00000200 INSTANCE 0 ADDRESS: 0x00000200 These bits read-protect flash in 16KB chunks.
PAGE 823
Apollo3 Blue Datasheet Table 1207: COPYPROTECTH Register Bits Bit Name Reset 31:0 CHUNKS 0xffffffff RW Description Copy (read) protect flash 0x00080000 - 0x000FFFFF. Each bit provides read protection for 16KB chunks of flash. 23.1.2.22WRITEPROTECTSBLL Register Flash write-protection bits. OFFSET: 0x000009F8 INSTANCE 0 ADDRESS: 0x000009F8 These bits write-protect flash in 16KB chunks.
PAGE 824
Apollo3 Blue Datasheet Table 1211: WRITEPROTECTSBLH Register Bits Bit Name Reset 31:0 CHUNKS 0xffffffff RW Description Write protect flash 0x00080000 - 0x000FFFFF. Each bit provides write protection for 16KB chunks of flash data space. 23.1.2.24COPYPROTECTSBLL Register Flash copy/read-protection bits. OFFSET: 0x00000A00 INSTANCE 0 ADDRESS: 0x00000A00 These bits read-protect flash in 16KB chunks.
PAGE 825
Apollo3 Blue Datasheet Table 1215: COPYPROTECTSBLH Register Bits Bit Name Reset 31:0 CHUNKS 0xffffffff RW Description Copy (read) protect flash 0x00080000 - 0x000FFFFF. Each bit provides read protection for 16KB chunks of flash. 23.1.2.
PAGE 826
Apollo3 Blue Datasheet Table 1219: MAINPTR1 Register Bits Bit Name Reset 31:0 PTR1 0xffffffff RW Description main pointer 1 23.1.2.28KREVTRACK Register KEK Revocation Tracker OFFSET: 0x00000C08 INSTANCE 0 ADDRESS: 0x00000C08 KEK Key Revocation Tracker. Monotonic counter where each bit indicates if that respective word in the KEK key bank is valid. For example, if KEK0 is not valid but KEK1-7 are valid (for a 128-bit KEK configuration), the KREVTRACK would be 0xFFFFFFF0.
PAGE 827
Apollo3 Blue Datasheet Table 1223: AREVTRACK Register Bits Bit Name Reset 31:0 ATRCKER 0xffffffff RW Description AUTH Revocation Tracker 23.1.2.30OTADESCRIPTOR Register OTA Descriptor Pointer OFFSET: 0x00000C10 INSTANCE 0 ADDRESS: 0x00000C10 This field is used to track the OTA DESCRIPTOR pointer to ensure proper OTA update.
PAGE 828
Apollo3 Blue Datasheet Table 1227: MAINCNT0 Register Bits Bit Name Reset 31:0 INDXCNTR 0xffffffff RW Description main Index Counter 23.1.2.32MAINCNT1 Register main Index Counter 1 OFFSET: 0x00000FFC INSTANCE 0 ADDRESS: 0x00000FFC Index counter for main or sbl_main firmware.
PAGE 829
Apollo3 Blue Datasheet Table 1231: CUSTKEKW0 Register Bits Bit Name Reset 31:0 CUSTKEK_W0 0xffffffff RW Description Customer KEK Word0 23.1.2.34CUSTKEKW1 Register Customer KEK Word1 OFFSET: 0x00001804 INSTANCE 0 ADDRESS: 0x00001804 This is the Customer KEK Word1.
PAGE 830
Apollo3 Blue Datasheet Table 1235: CUSTKEKW2 Register Bits Bit Name Reset 31:0 CUSTKEK_W2 0xffffffff RW Description Customer KEK Word2 23.1.2.36CUSTKEKW3 Register Customer KEK Word3 OFFSET: 0x0000180C INSTANCE 0 ADDRESS: 0x0000180C This is the Customer KEK Word3.
PAGE 831
Apollo3 Blue Datasheet Table 1239: CUSTKEKW4 Register Bits Bit Name Reset 31:0 CUSTKEK_W4 0xffffffff RW Description Customer KEK Word4 23.1.2.38CUSTKEKW5 Register Customer KEK Word5 OFFSET: 0x00001814 INSTANCE 0 ADDRESS: 0x00001814 This is the Customer KEK Word5.
PAGE 832
Apollo3 Blue Datasheet Table 1243: CUSTKEKW6 Register Bits Bit Name Reset 31:0 CUSTKEK_W6 0xffffffff RW Description Customer KEK Word6 23.1.2.40CUSTKEKW7 Register Customer KEK Word7 OFFSET: 0x0000181C INSTANCE 0 ADDRESS: 0x0000181C This is the Customer KEK Word7.
PAGE 833
Apollo3 Blue Datasheet Table 1247: CUSTKEKW8 Register Bits Bit Name Reset RW 31:0 CUSTKEK_W8 0xffffffff Description Customer KEK Word8 23.1.2.42CUSTKEKW9 Register Customer KEK Word9 OFFSET: 0x00001824 INSTANCE 0 ADDRESS: 0x00001824 This is the Customer KEK Word9.
PAGE 834
Apollo3 Blue Datasheet Table 1251: CUSTKEKW10 Register Bits Bit Name Reset RW 31:0 CUSTKEK_W10 0xffffffff Description Customer KEK Word10 23.1.2.44CUSTKEKW11 Register Customer KEK Word11 OFFSET: 0x0000182C INSTANCE 0 ADDRESS: 0x0000182C This is the Customer KEK Word11.
PAGE 835
Apollo3 Blue Datasheet Table 1255: CUSTKEKW12 Register Bits Bit Name Reset RW 31:0 CUSTKEK_W12 0xffffffff Description Customer KEK Word12 23.1.2.46CUSTKEKW13 Register Customer KEK Word13 OFFSET: 0x00001834 INSTANCE 0 ADDRESS: 0x00001834 This is the Customer KEK Word13.
PAGE 836
Apollo3 Blue Datasheet Table 1259: CUSTKEKW14 Register Bits Bit Name Reset RW 31:0 CUSTKEK_W14 0xffffffff Description Customer KEK Word14 23.1.2.48CUSTKEKW15 Register Customer KEK Word15 OFFSET: 0x0000183C INSTANCE 0 ADDRESS: 0x0000183C This is the Customer KEK Word15.
PAGE 837
Apollo3 Blue Datasheet Table 1263: CUSTKEKW16 Register Bits Bit Name Reset RW 31:0 CUSTKEK_W16 0xffffffff Description Customer KEK Word16 23.1.2.50CUSTKEKW17 Register Customer KEK Word17 OFFSET: 0x00001844 INSTANCE 0 ADDRESS: 0x00001844 This is the Customer KEK Word17.
PAGE 838
Apollo3 Blue Datasheet Table 1267: CUSTKEKW18 Register Bits Bit Name Reset RW 31:0 CUSTKEK_W18 0xffffffff Description Customer KEK Word18 23.1.2.52CUSTKEKW19 Register Customer KEK Word19 OFFSET: 0x0000184C INSTANCE 0 ADDRESS: 0x0000184C This is the Customer KEK Word19.
PAGE 839
Apollo3 Blue Datasheet Table 1271: CUSTKEKW20 Register Bits Bit Name Reset RW 31:0 CUSTKEK_W20 0xffffffff Description Customer KEK Word20 23.1.2.54CUSTKEKW21 Register Customer KEK Word21 OFFSET: 0x00001854 INSTANCE 0 ADDRESS: 0x00001854 This is the Customer KEK Word21.
PAGE 840
Apollo3 Blue Datasheet Table 1275: CUSTKEKW22 Register Bits Bit Name Reset RW 31:0 CUSTKEK_W22 0xffffffff Description Customer KEK Word22 23.1.2.56CUSTKEKW23 Register Customer KEK Word23 OFFSET: 0x0000185C INSTANCE 0 ADDRESS: 0x0000185C This is the Customer KEK Word23.
PAGE 841
Apollo3 Blue Datasheet Table 1279: CUSTKEKW24 Register Bits Bit Name Reset RW 31:0 CUSTKEK_W24 0xffffffff Description Customer KEK Word24 23.1.2.58CUSTKEKW25 Register Customer KEK Word25 OFFSET: 0x00001864 INSTANCE 0 ADDRESS: 0x00001864 This is the Customer KEK Word25.
PAGE 842
Apollo3 Blue Datasheet Table 1283: CUSTKEKW26 Register Bits Bit Name Reset RW 31:0 CUSTKEK_W26 0xffffffff Description Customer KEK Word26 23.1.2.60CUSTKEKW27 Register Customer KEK Word27 OFFSET: 0x0000186C INSTANCE 0 ADDRESS: 0x0000186C This is the Customer KEK Word27.
PAGE 843
Apollo3 Blue Datasheet Table 1287: CUSTKEKW28 Register Bits Bit Name Reset RW 31:0 CUSTKEK_W28 0xffffffff Description Customer KEK Word28 23.1.2.62CUSTKEKW29 Register Customer KEK Word29 OFFSET: 0x00001874 INSTANCE 0 ADDRESS: 0x00001874 This is the Customer KEK Word29.
PAGE 844
Apollo3 Blue Datasheet Table 1291: CUSTKEKW30 Register Bits Bit Name Reset RW 31:0 CUSTKEK_W30 0xffffffff Description Customer KEK Word30 23.1.2.64CUSTKEKW31 Register Customer KEK Word31 OFFSET: 0x0000187C INSTANCE 0 ADDRESS: 0x0000187C This is the Customer KEK Word31.
PAGE 845
Apollo3 Blue Datasheet Table 1295: CUSTAUTHW0 Register Bits Bit Name Reset 31:0 CUSTAUTH_W0 0xffffffff RW Description Customer AUTH Key Word0 23.1.2.66CUSTAUTHW1 Register Customer AUTH Key Word1 OFFSET: 0x00001884 INSTANCE 0 ADDRESS: 0x00001884 This is the Customer AUTH Key Word1.
PAGE 846
Apollo3 Blue Datasheet Table 1299: CUSTAUTHW2 Register Bits Bit Name Reset 31:0 CUSTAUTH_W2 0xffffffff RW Description Customer AUTH Key Word2 23.1.2.68CUSTAUTHW3 Register Customer AUTH Key Word3 OFFSET: 0x0000188C INSTANCE 0 ADDRESS: 0x0000188C This is the Customer AUTH Key Word3.
PAGE 847
Apollo3 Blue Datasheet Table 1303: CUSTAUTHW4 Register Bits Bit Name Reset 31:0 CUSTAUTH_W4 0xffffffff RW Description Customer AUTH Key Word4 23.1.2.70CUSTAUTHW5 Register Customer AUTH Key Word5 OFFSET: 0x00001894 INSTANCE 0 ADDRESS: 0x00001894 This is the Customer AUTH Key Word5.
PAGE 848
Apollo3 Blue Datasheet Table 1307: CUSTAUTHW6 Register Bits Bit Name Reset 31:0 CUSTAUTH_W6 0xffffffff RW Description Customer AUTH Key Word6 23.1.2.72CUSTAUTHW7 Register Customer AUTH Key Word7 OFFSET: 0x0000189C INSTANCE 0 ADDRESS: 0x0000189C This is the Customer AUTH Key Word7.
PAGE 849
Apollo3 Blue Datasheet Table 1311: CUSTAUTHW8 Register Bits Bit Name Reset 31:0 CUSTAUTH_W8 0xffffffff RW Description Customer AUTH Key Word8 23.1.2.74CUSTAUTHW9 Register Customer AUTH Key Word9 OFFSET: 0x000018A4 INSTANCE 0 ADDRESS: 0x000018A4 This is the Customer AUTH Key Word9.
PAGE 850
Apollo3 Blue Datasheet Table 1315: CUSTAUTHW10 Register Bits Bit Name Reset 31:0 CUSTAUTH_W10 0xffffffff RW Description Customer AUTH Key Word10 23.1.2.76CUSTAUTHW11 Register Customer AUTH Key Word11 OFFSET: 0x000018AC INSTANCE 0 ADDRESS: 0x000018AC This is the Customer AUTH Key Word11.
PAGE 851
Apollo3 Blue Datasheet Table 1319: CUSTAUTHW12 Register Bits Bit Name Reset 31:0 CUSTAUTH_W12 0xffffffff RW Description Customer AUTH Key Word12 23.1.2.78CUSTAUTHW13 Register Customer AUTH Key Word13 OFFSET: 0x000018B4 INSTANCE 0 ADDRESS: 0x000018B4 This is the Customer AUTH Key Word13.
PAGE 852
Apollo3 Blue Datasheet Table 1323: CUSTAUTHW14 Register Bits Bit Name Reset 31:0 CUSTAUTH_W14 0xffffffff RW Description Customer AUTH Key Word14 23.1.2.80CUSTAUTHW15 Register Customer AUTH Key Word15 OFFSET: 0x000018BC INSTANCE 0 ADDRESS: 0x000018BC This is the Customer AUTH Key Word15.
PAGE 853
Apollo3 Blue Datasheet Table 1327: CUSTAUTHW16 Register Bits Bit Name Reset 31:0 CUSTAUTH_W16 0xffffffff RW Description Customer AUTH Key Word16 23.1.2.82CUSTAUTHW17 Register Customer AUTH Key Word17 OFFSET: 0x000018C4 INSTANCE 0 ADDRESS: 0x000018C4 This is the Customer AUTH Key Word17.
PAGE 854
Apollo3 Blue Datasheet Table 1331: CUSTAUTHW18 Register Bits Bit Name Reset 31:0 CUSTAUTH_W18 0xffffffff RW Description Customer AUTH Key Word18 23.1.2.84CUSTAUTHW19 Register Customer AUTH Key Word19 OFFSET: 0x000018CC INSTANCE 0 ADDRESS: 0x000018CC This is the Customer AUTH Key Word19.
PAGE 855
Apollo3 Blue Datasheet Table 1335: CUSTAUTHW20 Register Bits Bit Name Reset 31:0 CUSTAUTH_W20 0xffffffff RW Description Customer AUTH Key Word20 23.1.2.86CUSTAUTHW21 Register Customer AUTH Key Word21 OFFSET: 0x000018D4 INSTANCE 0 ADDRESS: 0x000018D4 This is the Customer AUTH Key Word21.
PAGE 856
Apollo3 Blue Datasheet Table 1339: CUSTAUTHW22 Register Bits Bit Name Reset 31:0 CUSTAUTH_W22 0xffffffff RW Description Customer AUTH Key Word22 23.1.2.88CUSTAUTHW23 Register Customer AUTH Key Word23 OFFSET: 0x000018DC INSTANCE 0 ADDRESS: 0x000018DC This is the Customer AUTH Key Word23.
PAGE 857
Apollo3 Blue Datasheet Table 1343: CUSTAUTHW24 Register Bits Bit Name Reset 31:0 CUSTAUTH_W24 0xffffffff RW Description Customer AUTH Key Word24 23.1.2.90CUSTAUTHW25 Register Customer AUTH Key Word25 OFFSET: 0x000018E4 INSTANCE 0 ADDRESS: 0x000018E4 This is the Customer AUTH Key Word25.
PAGE 858
Apollo3 Blue Datasheet Table 1347: CUSTAUTHW26 Register Bits Bit Name Reset 31:0 CUSTAUTH_W26 0xffffffff RW Description Customer AUTH Key Word26 23.1.2.92CUSTAUTHW27 Register Customer AUTH Key Word27 OFFSET: 0x000018EC INSTANCE 0 ADDRESS: 0x000018EC This is the Customer AUTH Key Word27.
PAGE 859
Apollo3 Blue Datasheet Table 1351: CUSTAUTHW28 Register Bits Bit Name Reset 31:0 CUSTAUTH_W28 0xffffffff RW Description Customer AUTH Key Word28 23.1.2.94CUSTAUTHW29 Register Customer AUTH Key Word29 OFFSET: 0x000018F4 INSTANCE 0 ADDRESS: 0x000018F4 This is the Customer AUTH Key Word29.
PAGE 860
Apollo3 Blue Datasheet Table 1355: CUSTAUTHW30 Register Bits Bit Name Reset 31:0 CUSTAUTH_W30 0xffffffff RW Description Customer AUTH Key Word30 23.1.2.96CUSTAUTHW31 Register Customer AUTH Key Word31 OFFSET: 0x000018FC INSTANCE 0 ADDRESS: 0x000018FC This is the Customer AUTH Key Word31.
PAGE 861
Apollo3 Blue Datasheet Table 1359: CUSTPUBKEYW0 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W0 0xffffffff RW Description Customer Public Key Word0 23.1.2.98CUSTPUBKEYW1 Register Customer Public Key Word1 OFFSET: 0x00001904 INSTANCE 0 ADDRESS: 0x00001904 This is the Customer Public Key Word1.
PAGE 862
Apollo3 Blue Datasheet Table 1363: CUSTPUBKEYW2 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W2 0xffffffff RW Description Customer Public Key Word2 23.1.2.100CUSTPUBKEYW3 Register Customer Public Key Word3 OFFSET: 0x0000190C INSTANCE 0 ADDRESS: 0x0000190C This is the Customer Public Key Word3.
PAGE 863
Apollo3 Blue Datasheet Table 1367: CUSTPUBKEYW4 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W4 0xffffffff RW Description Customer Public Key Word4 23.1.2.102CUSTPUBKEYW5 Register Customer Public Key Word5 OFFSET: 0x00001914 INSTANCE 0 ADDRESS: 0x00001914 This is the Customer Public Key Word5.
PAGE 864
Apollo3 Blue Datasheet Table 1371: CUSTPUBKEYW6 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W6 0xffffffff RW Description Customer Public Key Word6 23.1.2.104CUSTPUBKEYW7 Register Customer Public Key Word7 OFFSET: 0x0000191C INSTANCE 0 ADDRESS: 0x0000191C This is the Customer Public Key Word7.
PAGE 865
Apollo3 Blue Datasheet Table 1375: CUSTPUBKEYW8 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W8 0xffffffff RW Description Customer Public Key Word8 23.1.2.106CUSTPUBKEYW9 Register Customer Public Key Word9 OFFSET: 0x00001924 INSTANCE 0 ADDRESS: 0x00001924 This is the Customer Public Key Word9.
PAGE 866
Apollo3 Blue Datasheet Table 1379: CUSTPUBKEYW10 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W10 0xffffffff RW Description Customer Public Key Word10 23.1.2.108CUSTPUBKEYW11 Register Customer Public Key Word11 OFFSET: 0x0000192C INSTANCE 0 ADDRESS: 0x0000192C This is the Customer Public Key Word11.
PAGE 867
Apollo3 Blue Datasheet Table 1383: CUSTPUBKEYW12 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W12 0xffffffff RW Description Customer Public Key Word12 23.1.2.110CUSTPUBKEYW13 Register Customer Public Key Word13 OFFSET: 0x00001934 INSTANCE 0 ADDRESS: 0x00001934 This is the Customer Public Key Word13.
PAGE 868
Apollo3 Blue Datasheet Table 1387: CUSTPUBKEYW14 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W14 0xffffffff RW Description Customer Public Key Word14 23.1.2.112CUSTPUBKEYW15 Register Customer Public Key Word15 OFFSET: 0x0000193C INSTANCE 0 ADDRESS: 0x0000193C This is the Customer Public Key Word15.
PAGE 869
Apollo3 Blue Datasheet Table 1391: CUSTPUBKEYW16 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W16 0xffffffff RW Description Customer Public Key Word16 23.1.2.114CUSTPUBKEYW17 Register Customer Public Key Word17 OFFSET: 0x00001944 INSTANCE 0 ADDRESS: 0x00001944 This is the Customer Public Key Word17.
PAGE 870
Apollo3 Blue Datasheet Table 1395: CUSTPUBKEYW18 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W18 0xffffffff RW Description Customer Public Key Word18 23.1.2.116CUSTPUBKEYW19 Register Customer Public Key Word19 OFFSET: 0x0000194C INSTANCE 0 ADDRESS: 0x0000194C This is the Customer Public Key Word19.
PAGE 871
Apollo3 Blue Datasheet Table 1399: CUSTPUBKEYW20 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W20 0xffffffff RW Description Customer Public Key Word20 23.1.2.118CUSTPUBKEYW21 Register Customer Public Key Word21 OFFSET: 0x00001954 INSTANCE 0 ADDRESS: 0x00001954 This is the Customer Public Key Word21.
PAGE 872
Apollo3 Blue Datasheet Table 1403: CUSTPUBKEYW22 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W22 0xffffffff RW Description Customer Public Key Word22 23.1.2.120CUSTPUBKEYW23 Register Customer Public Key Word23 OFFSET: 0x0000195C INSTANCE 0 ADDRESS: 0x0000195C This is the Customer Public Key Word23.
PAGE 873
Apollo3 Blue Datasheet Table 1407: CUSTPUBKEYW24 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W24 0xffffffff RW Description Customer Public Key Word24 23.1.2.122CUSTPUBKEYW25 Register Customer Public Key Word25 OFFSET: 0x00001964 INSTANCE 0 ADDRESS: 0x00001964 This is the Customer Public Key Word25.
PAGE 874
Apollo3 Blue Datasheet Table 1411: CUSTPUBKEYW26 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W26 0xffffffff RW Description Customer Public Key Word26 23.1.2.124CUSTPUBKEYW27 Register Customer Public Key Word27 OFFSET: 0x0000196C INSTANCE 0 ADDRESS: 0x0000196C This is the Customer Public Key Word27.
PAGE 875
Apollo3 Blue Datasheet Table 1415: CUSTPUBKEYW28 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W28 0xffffffff RW Description Customer Public Key Word28 23.1.2.126CUSTPUBKEYW29 Register Customer Public Key Word29 OFFSET: 0x00001974 INSTANCE 0 ADDRESS: 0x00001974 This is the Customer Public Key Word29.
PAGE 876
Apollo3 Blue Datasheet Table 1419: CUSTPUBKEYW30 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W30 0xffffffff RW Description Customer Public Key Word30 23.1.2.128CUSTPUBKEYW31 Register Customer Public Key Word31 OFFSET: 0x0000197C INSTANCE 0 ADDRESS: 0x0000197C This is the Customer Public Key Word31.
PAGE 877
Apollo3 Blue Datasheet Table 1423: CUSTPUBKEYW32 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W32 0xffffffff RW Description Customer Public Key Word32 23.1.2.130CUSTPUBKEYW33 Register Customer Public Key Word33 OFFSET: 0x00001984 INSTANCE 0 ADDRESS: 0x00001984 This is the Customer Public Key Word33.
PAGE 878
Apollo3 Blue Datasheet Table 1427: CUSTPUBKEYW34 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W34 0xffffffff RW Description Customer Public Key Word34 23.1.2.132CUSTPUBKEYW35 Register Customer Public Key Word35 OFFSET: 0x0000198C INSTANCE 0 ADDRESS: 0x0000198C This is the Customer Public Key Word35.
PAGE 879
Apollo3 Blue Datasheet Table 1431: CUSTPUBKEYW36 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W36 0xffffffff RW Description Customer Public Key Word36 23.1.2.134CUSTPUBKEYW37 Register Customer Public Key Word37 OFFSET: 0x00001994 INSTANCE 0 ADDRESS: 0x00001994 This is the Customer Public Key Word37.
PAGE 880
Apollo3 Blue Datasheet Table 1435: CUSTPUBKEYW38 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W38 0xffffffff RW Description Customer Public Key Word38 23.1.2.136CUSTPUBKEYW39 Register Customer Public Key Word39 OFFSET: 0x0000199C INSTANCE 0 ADDRESS: 0x0000199C This is the Customer Public Key Word39.
PAGE 881
Apollo3 Blue Datasheet Table 1439: CUSTPUBKEYW40 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W40 0xffffffff RW Description Customer Public Key Word40 23.1.2.138CUSTPUBKEYW41 Register Customer Public Key Word41 OFFSET: 0x000019A4 INSTANCE 0 ADDRESS: 0x000019A4 This is the Customer Public Key Word41.
PAGE 882
Apollo3 Blue Datasheet Table 1443: CUSTPUBKEYW42 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W42 0xffffffff RW Description Customer Public Key Word42 23.1.2.140CUSTPUBKEYW43 Register Customer Public Key Word43 OFFSET: 0x000019AC INSTANCE 0 ADDRESS: 0x000019AC This is the Customer Public Key Word43.
PAGE 883
Apollo3 Blue Datasheet Table 1447: CUSTPUBKEYW44 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W44 0xffffffff RW Description Customer Public Key Word44 23.1.2.142CUSTPUBKEYW45 Register Customer Public Key Word45 OFFSET: 0x000019B4 INSTANCE 0 ADDRESS: 0x000019B4 This is the Customer Public Key Word45.
PAGE 884
Apollo3 Blue Datasheet Table 1451: CUSTPUBKEYW46 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W46 0xffffffff RW Description Customer Public Key Word46 23.1.2.144CUSTPUBKEYW47 Register Customer Public Key Word47 OFFSET: 0x000019BC INSTANCE 0 ADDRESS: 0x000019BC This is the Customer Public Key Word47.
PAGE 885
Apollo3 Blue Datasheet Table 1455: CUSTPUBKEYW48 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W48 0xffffffff RW Description Customer Public Key Word48 23.1.2.146CUSTPUBKEYW49 Register Customer Public Key Word49 OFFSET: 0x000019C4 INSTANCE 0 ADDRESS: 0x000019C4 This is the Customer Public Key Word49.
PAGE 886
Apollo3 Blue Datasheet Table 1459: CUSTPUBKEYW50 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W50 0xffffffff RW Description Customer Public Key Word50 23.1.2.148CUSTPUBKEYW51 Register Customer Public Key Word51 OFFSET: 0x000019CC INSTANCE 0 ADDRESS: 0x000019CC This is the Customer Public Key Word51.
PAGE 887
Apollo3 Blue Datasheet Table 1463: CUSTPUBKEYW52 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W52 0xffffffff RW Description Customer Public Key Word52 23.1.2.150CUSTPUBKEYW53 Register Customer Public Key Word53 OFFSET: 0x000019D4 INSTANCE 0 ADDRESS: 0x000019D4 This is the Customer Public Key Word53.
PAGE 888
Apollo3 Blue Datasheet Table 1467: CUSTPUBKEYW54 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W54 0xffffffff RW Description Customer Public Key Word54 23.1.2.152CUSTPUBKEYW55 Register Customer Public Key Word55 OFFSET: 0x000019DC INSTANCE 0 ADDRESS: 0x000019DC This is the Customer Public Key Word55.
PAGE 889
Apollo3 Blue Datasheet Table 1471: CUSTPUBKEYW56 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W56 0xffffffff RW Description Customer Public Key Word56 23.1.2.154CUSTPUBKEYW57 Register Customer Public Key Word57 OFFSET: 0x000019E4 INSTANCE 0 ADDRESS: 0x000019E4 This is the Customer Public Key Word57.
PAGE 890
Apollo3 Blue Datasheet Table 1475: CUSTPUBKEYW58 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W58 0xffffffff RW Description Customer Public Key Word58 23.1.2.156CUSTPUBKEYW59 Register Customer Public Key Word59 OFFSET: 0x000019EC INSTANCE 0 ADDRESS: 0x000019EC This is the Customer Public Key Word59.
PAGE 891
Apollo3 Blue Datasheet Table 1479: CUSTPUBKEYW60 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W60 0xffffffff RW Description Customer Public Key Word60 23.1.2.158CUSTPUBKEYW61 Register Customer Public Key Word61 OFFSET: 0x000019F4 INSTANCE 0 ADDRESS: 0x000019F4 This is the Customer Public Key Word61.
PAGE 892
Apollo3 Blue Datasheet Table 1483: CUSTPUBKEYW62 Register Bits Bit Name Reset 31:0 CUSTPUBKEY_W62 0xffffffff RW Description Customer Public Key Word62 23.1.2.160CUSTPUBKEYW63 Register Customer Public Key Word63 OFFSET: 0x000019FC INSTANCE 0 ADDRESS: 0x000019FC This is the Customer Public Key Word63.
PAGE 893
Apollo3 Blue Datasheet Table 1487: CUSTOMERKEY0 Register Bits Bit Name Reset 31:0 CHUNKS 0xffffffff RW Description Word 0 of the customer key. 23.1.2.162CUSTOMERKEY1 Register 128-bit customer key.
PAGE 894
Apollo3 Blue Datasheet Table 1491: CUSTOMERKEY2 Register Bits Bit Name Reset 31:0 CHUNKS 0xffffffff RW Description Word 2 of the customer key. 23.1.2.164CUSTOMERKEY3 Register 128-bit customer key.
PAGE 895
Apollo3 Blue Datasheet Table 1495: CUSTPUBHASHW0 Register Bits Bit Name Reset 31:0 CUSTPUBHASH_W0 0xffffffff RW Description Customer Public Key Hash Word0 23.1.2.166CUSTPUBHASHW1 Register Customer Public Key Hash Word1 OFFSET: 0x00001A14 INSTANCE 0 ADDRESS: 0x00001A14 This is the Customer Public Key Hash Word1.
PAGE 896
Apollo3 Blue Datasheet Table 1499: CUSTPUBHASHW2 Register Bits Bit Name Reset 31:0 CUSTPUBHASH_W2 0xffffffff RW Description Customer Public Key Hash Word2 23.1.2.168CUSTPUBHASHW3 Register Customer Public Key Hash Word3 OFFSET: 0x00001A1C INSTANCE 0 ADDRESS: 0x00001A1C This is the Customer Public Key Hash Word3.
PAGE 897
Apollo3 Blue Datasheet Index Numerics 10BIT 271 12/24 Hour Mode 548 3-wire mode 274 A Access permissions 73 accumulation control 726 accumulation, automatic 726 ACK 271, 333 Acknowledge 271 Active Mode 75, 528 ADC 67, 357, 406, 723 ADC Configuration Register 732 ADC Reference Generator 725 ADC_DIV3 724 ADC_EXT0 724 ADC_EXT1 724 ADC_EXT2 724 ADC_EXT6 724 ADC_EXT7 724 ADCREF 406 ADC_SWT 725 ADC_TEMP 724 ADC_TRIG0 725 ADC_TRIG1 725 ADC_VSS 724 AHB 74, 325 Alarm Registers 548 ALM interrupt 548 ALM100 548 AM08X
PAGE 898
Apollo3 Blue Datasheet B Bandgap 725 battery life 66 BCD format 547 Buck Converters 771 Bus Not Busy 270, 333 bus, AMBA AHB 74 bus, AMBA APB 74 bus, DCode 74 bus, ICode 74 bus, System 74 C Calibration, Distributed Digital 525, 526 CALRC 525 CALXT 526 CLKOUT 523, 525, 528 Clock Generator Module 523 clock sources 67 clock, interface 268 CMPOUT 764 CMPR0 559, 560 CMPR1 560 CONT 274 Continuous 561, 562 control, accumulation 726 converters, buck 771 core, see processor Cortex, see processor counter, 32-bit 563
PAGE 899
Apollo3 Blue Datasheet event 68 event, wakeup 74 F Fast Mode Plus 332 fault handler, Memanage 73 Faulting Address Trapping Hardware 94 FIFO 326, 723 Area Functions 329 FIFOCTR 329 FIFOPTR 329 FIFOREM 270 FIFORTHR 270 FIFOSIZ 270, 329 FIFOUPD 331 FIFOWTHR 270 flash 67 G GPIO 386 GPIO and Pad Configuration Module 379 GPIOA_IER 386 GPIOA_ISR 386 GPIOA_WCR 386 GPIOB_IER 386 GPIOB_ISR 386 GPIOB_WCR 386 GPIOB_WSR 386 GPIOEN 386 GPIOENA 386 GPIOENB 386 GPIOnINCFG 386, 389 GPIOn_INT 389 GPIOnINTD 389 GPIOnINTP 386
PAGE 900
Apollo3 Blue Datasheet HFADJCK 527 HFRC 526, 724 HFRC Autoadjustment 527 HFXTADJ 527 High Frequency RC Oscillator 526 HR1224 548 I I2C 10-bit addressing 334 7-bit addressing 334 ADDRESS 271 Address 334 Command 271 FIFO 270 I2CADDR 332, 334 IO Master 0 389 IO Master 1 390, 391 IO Slave 397 master 258 Multi-master Arbitration 274 Normal Read 273 Normal Write 272 Offset Address 272, 334 Raw Read 273 Raw Write 273 Read 335 receiver 270 SCL 270 SDA 270 Slave 325, 332 transmitter 270 Write 335 I2C/SPI Master 524
PAGE 901
Apollo3 Blue Datasheet IOINT 331 IOREAD 331 ITM, see Instrumentation Trace Macrocell L LDO 771 LFRC 524, 529 life, battery 66 Low-Power Consumption Modes 68 M Managed Conversion Slots 725 map, memory 71 Master Module , I2C/SPI 173, 216, 258 MemManage 73 memory 67 LRAM 270, 325 RAM 67 SRAM 74 memory map 71 peripheral device 72 Memory Protection Unit 73 MISO 274 mode Active 75 Deep Sleep 75, 524 Sleep 75 mode, Deep Sleep 74 Module, ADC and Temperature Sensor 723 module, PINCFG 274 MOSI 274 MPU, see Memory Pr
PAGE 902
Apollo3 Blue Datasheet P PAD10PULL 392, 393 PAD20FNCSEL 408 PAD20INPEN 408 PAD21INPEN 408 PAD5INPEN 389, 391 PAD5PULL 389, 391 PAD5RSEL 389 PAD6INPEN 389, 391 PAD6PULL 389, 391 PAD6RSEL 390 PAD7PULL 391 PAD8INPEN 390, 391, 392, 393 PAD8PULL 390, 391, 392, 393 PAD9INPEN 390, 391, 392, 393 PAD9PULL 390, 391, 392, 393 PADKEY 386 PADnFNCSEL 379–??, 386 PADnINPEN 389, 392, 393, 399, 401, 403, 404, 405 PADnPULL 380, 389, 392, 393, 399, 401, 403, 404, 405 PADnRSEL 389 Peripheral Device Memory Map 72 PINCFG 274 po
PAGE 903
Apollo3 Blue Datasheet REG_CLK_GEN_CTRLOW_CTRHR 547 REG_CLK_GEN_CTRLOW_CTRMIN 547 REG_CLK_GEN_CTRLOW_CTRSEC 547 REG_CLK_GEN_CTRUP_CB 547 REG_CLK_GEN_CTRUP_CEB 548 REG_CLK_GEN_CTRUP_CTRDATE 547 REG_CLK_GEN_CTRUP_CTRERR 547 REG_CLK_GEN_CTRUP_CTRMO 547 REG_CLK_GEN_CTRUP_CTRWKDY 547 REG_CLK_GEN_CTRUP_CTRYR 547 REG_CLKGEN_HFTUNERB 527 REG_CLKGEN_OCTRL_OSEL 525, 526 REG_CLK_GEN_RTCCTL_HR1224 548 REG_CLK_GEN_RTCCTL_RPT 548 REG_CLK_GEN_RTCCTL_RSTOP 547 REG_CLK_GEN_RTCCTL_WRTC 547 REG_CLKGEN_STATUS_OMODE 526 REG_CL
PAGE 904
Apollo3 Blue Datasheet REG_IOMSTRn_FIFOPTR_FIFOSIZ 270 REG_IOMSTRn_FIFOTHR_FIFOWTHR 269 REG_IOMSTRn_IOMCFG_SPHA 274 REG_IOMSTRn_IOMCFG_SPOL 274 REG_IOSLAVE_FIFOCFG_FIFOBASE 325, 326 REG_IOSLAVE_FIFOCFG_FIFOMAX 326 REG_IOSLAVE_FIFOCFG_ROBASE 329 REG_IOSLAVE_FIFOCTR 329 REG_IOSLAVE_FIFOPTR_FIFOPTR 329 REG_IOSLAVE_FUPD_FIFOUPD 331 REG_IOSLAVE_FUPD_IOREAD 331 REG_IOSLAVE_IOSCFG_I2CADDR 332 REG_IOSLAVE_IOSCFG_LSB 338 REG_IOSLAVE_PRENC 328 Repeated Count 559 Repeated Pulse 560 Reset Module 698 reset, power-on 74
PAGE 905
Apollo3 Blue Datasheet OPER 275 Phase 277 Polarity 277 Raw Read 276 Raw Write 276 Read 337 Slave 325, 336 slave 336 Slave Addressing 275 Write 336 SPOL 277, 338 START 333 Start Data Transfer 271, 333 STOP 274, 333 STOP condition 271 Stop Data Transfer 271, 333 Successive Approximation Register 67, 723 SWD, see Serial Wire Debug SWD, see Serial Wire Debugger SWDCK 408 SWDIO 408 SYSRESETREQn 698 System Control Register 75 T Temperature Sensor 723 TMRWCR 558, 559 TPIU, see Trace Port Interface Unit Trace Port
PAGE 906
Apollo3 Blue Datasheet VTEMP 764 W Wait-For-Interrupt 75 Wakeup 338 wake-up 67 Wake-Up Interrupt Controller 74 Watchdog Timer 690 WC bit 558 WDTCFG 690 WFI, see Wait-For-Interrupt WIC, see wake-up Window Comparisons 726 X XT 525, 529 XT Oscillator 525 DS-A3-0p9p1 Page 906 of 909 2019 Ambiq Micro, Inc. All rights reserved.
PAGE 907
Apollo3 Blue Datasheet 909 24. Ordering Information Table 1502: Ordering Information Orderable Part Number Flash RAM Package Packing Temperature Range Availability AMA3B1KK-KBR 1 MB 384 KB 81-pin BGA Tape and Reel –40 to 85°C Now AMA3B1KK-KCR 1 MB 384 KB 66-pin CSP Tape and Reel –40 to 85°C Apr 2019 DS-A3-0p9p1 Page 907 of 909 2019 Ambiq Micro, Inc. All rights reserved.
PAGE 908
Apollo3 Blue Datasheet 909 25. Document Revision History Table 1503: Document Revision List Revision Date 0.6 Feb 2018 Initial alpha release - Updated Appendix 0.
PAGE 909
Apollo3 Blue Datasheet 909 Contact Information Address Ambiq Micro, Inc. 6500 River Place Blvd. Building 7, Suite 200 Austin, TX 78730-1156 Phone +1 (512) 879-2850 Website https://ambiqmicro.com/ General Information info@ambiqmicro.com Sales sales@ambiqmicro.com Technical Support https://support.ambiqmicro.com Legal Information and Disclaimers AMBIQ MICRO INTENDS FOR THE CONTENT CONTAINED IN THE DOCUMENT TO BE ACCURATE AND RELIABLE.