Datasheet

VS1053b Datasheet
11 VS1053B REGISTERS
11.14 I2S DAC Interface
The 16-bit I2S Interface makes it possible to attach an external DAC to the system.
Note: The samplerate of the audio file and the I2S rate are independent. All audio will be
automatically converted to 6.144 MHz for VS1053 DAC and to the configured I2S rate using a
high-quality sample-rate converter.
Note: In VS1053b the I2S pins share different GPIO pins than in VS1033 to be able to use SPI
boot and I2S in the same application.
I2S registers, prefix I2S_
Reg Type Reset Abbrev Description
0xC040 r/w 0 CONFIG[3:0] I2S configuration
I2S_CONFIG Bits
Name Bits Description
I2S_CF_MCLK_ENA 3 Enables the MCLK output (12.288 MHz)
I2S_CF_ENA 2 Enables I2S, otherwise pins are GPIO
I2S_CF_SRATE 1:0 I2S rate, "10" = 192, "01" = 96, "00" = 48 kHz
I2S_CF_ENA enables the I2S interface. After reset I2S is disabled and the pins are used for
GPIO inputs.
I2S_CF_MCLK_ENA enables the MCLK output. The frequency is either directly the input clock
(nominal 12.288 MHz), or half the input clock when mode register bit SM_CLK_RANGE is set
to 1 (24-26 MHz input clock).
I2S_CF_SRATE controls the output samplerate. When set to 48 kHz, SCLK is MCLK divided
by 8, when 96 kHz SCLK is MCLK divided by 4, and when 192 kHz SCLK is MCLK divided by
2. I2S_CF_SRATE can only be changed when I2S_CF_ENA is 0.
MCLK
SDATA
SCLK
LROUT
MSB LSB MSB
Left Channel Word Right Channel Word
Figure 21: I2S interface, 192 kHz.
To enable I2S first write 0xc017 to SCI_WRAMADDR and 0x00f0 to SCI_WRAM, then write
0xc040 to SCI_WRAMADDR and 0x000c to SCI_WRAM.
Version: 1.22, 2014-12-19 82