Datasheet

VS1053b Datasheet
11 VS1053B REGISTERS
11.13.3 Configuration TIMER_ENABLE
TIMER_ENABLE Bits
Name Bits Description
TIMER_EN_T1 1 Enable timer 1
TIMER_EN_T0 0 Enable timer 0
11.13.4 Timer X Startvalue TIMER_Tx[L/H]
The 32-bit start value TIMER_Tx[L/H] sets the initial counter value when the timer is reset. The
timer interrupt frequency f
t
=
f
i
c+1
where f
i
is the master clock obtained with the clock divider
(see Chapter 11.13.2 and c is TIMER_Tx[L/H].
Example: With a 12 MHz master clock and with TIMER_CF_CLKDIV=3, the master clock f
i
=
3MHz. If TIMER_TH=0, TIMER_TL=99, then the timer interrupt frequency f
t
=
3MHz
99+1
=
30kHz.
11.13.5 Timer X Counter TIMER_TxCNT[L/H]
TIMER_TxCNT[L/H] contains the current counter values. By reading this register pair, the user
may get knowledge of how long it will take before the next timer interrupt. Also, by writing to
this register, a one-shot different length timer interrupt delay may be realized.
11.13.6 Timer Interrupts
Each timer has its own interrupt, which is asserted when the timer counter underflows.
Version: 1.22, 2014-12-19 81