Datasheet

VS1053b Datasheet
11 VS1053B REGISTERS
Example UART Speeds, f
m
= 49.152 MHz
Comm. Speed [bps] UART_DIV_D1 UART_DIV_D2
4800 255 40
9600 255 20
14400 233 15
19200 255 10
28800 243 7
38400 159 8
57600 121 7
115200 60 7
11.12.6 UART Interrupts and Operation
Transmitter operates as follows: After an 8-bit word is written to the transmit data register it will
be transmitted instantly if the transmitter is not busy transmitting the previous byte. When the
transmission begins a TX_INTR interrupt will be sent. Status bit [1] informs the transmitter data
register empty (or full state) and bit [0] informs the transmitter (shift register) empty state. A
new word must not be written to transmitter data register if it is not empty (bit [1] = ’0’). The
transmitter data register will be empty as soon as it is shifted to transmitter and the transmission
is begun. It is safe to write a new word to transmitter data register every time a transmit interrupt
is generated.
Receiver operates as follows: It samples the RX signal line and if it detects a high to low
transition, a start bit is found. After this it samples each 8 bit at the middle of the bit time (using
a constant timer), and fills the receiver (shift register) LSB first. Finally the data in the receiver
is moved to the reveive data register, the stop bit state is checked (logic high = ok, logic low =
framing error) for status bit[4], the RX_INTR interrupt is sent, status bit[2] (receive data register
full) is set, and status bit[2] old state is copied to bit[3] (receive data overrun). After that the
receiver returns to idle state to wait for a new start bit. Status bit[2] is zeroed when the receiver
data register is read.
RS232 communication speed is set using two clock dividers. The base clock is the processor
master clock. Bits 15-8 in these registers are for first divider and bits 7-0 for second divider. RX
sample frequency is the clock frequency that is input for the second divider.
Version: 1.22, 2014-12-19 79