Datasheet

VS1053b Datasheet
11 VS1053B REGISTERS
UART_ST_TXRUNNING is set if the transmitter shift register is in operation.
11.12.3 Data UART_DATA
A read from UART_DATA returns the received byte in bits 7:0, bits 15:8 are returned as ’0’. If
there is no more data to be read, the receiver data register full indicator will be cleared.
A receive interrupt will be generated when a byte is moved from the receiver shift register to
the receiver data register.
A write to UART_DATA sets a byte for transmission. The data is taken from bits 7:0, other
bits in the written value are ignored. If the transmitter is idle, the byte is immediately moved
to the transmitter shift register, a transmit interrupt request is generated, and transmission is
started. If the transmitter is busy, the UART_ST_TXFULL will be set and the byte remains in the
transmitter data register until the previous byte has been sent and transmission can proceed.
11.12.4 Data High UART_DATAH
The same as UART_DATA, except that bits 15:8 are used.
11.12.5 Divider UART_DIV
UART_DIV Bits
Name Bits Description
UART_DIV_D1 15:8 Divider 1 (0..255)
UART_DIV_D2 7:0 Divider 2 (6..255)
The divider is set to 0x0000 in reset. The ROM boot code must initialize it correctly depending
on the master clock frequency to get the correct bit speed. The second divider (D
2
) must be
from 6 to 255.
The communication speed f =
f
m
(D
1
+1)×(D
2
)
, where f
m
is the master clock frequency, and f is
the TX/RX speed in bps.
Divider values for common communication speeds at 26 MHz master clock:
Version: 1.22, 2014-12-19 78