Datasheet

VS1053b Datasheet
11 VS1053B REGISTERS
• Select PLL clock multiplier
At the core of the PLL controller is the VCO, a high frequency oscillator, whose oscillation
frequency is adjusted to be an integer multiple of some input frequency. As the name “Phase-
Locked Loop” suggests, this is done by comparing the phase of the input frequency against the
phase of a signal which is derived from the VCO output through frequency division.
If the system is stable, e.g. the comparison phase difference remains virtually zero, the PLL is
said to be “in lock”. This means that the output frequency of the VCO is stable and reliable.
The PLL is preceded by a division-by-two unit. Thus, with a nominal XTALI = 12.288 MHz, the
internal clock frequency CLKI can be adjusted with an accuracy of XTALI/2 = 6.144 MHz.
PLL control lies in DAC_FCTL bits 13:4. To see what bits 3:0 do, see Chapter 11.8.
FREQCTLH PLL bits, prefix FCH_
Name Bits Description
PLL_LOCKED 13 0=lock failed since last test (read-only)
PLL_SET_LOCK 12 1:Sets FCH_PLL_LOCKED to 1 to start lock test
PLL_VCO_OUT_ENA 11 Route VCO to GPIO pin (VS1000:second cs pin)
PLL_FORCE_PLL 9 1:System clock is VCO / 0:System clock is inclk
PLL_DIV_INCLK 8 divide inclk by 2 (for 1.5, 2.5 or 3.5 x clk)
PLL_RATE 7:4 PLL rate control
The PLL locked status can be checked by generating a high-active pulse (writing first “1” , then
“0”) to FCH_PLL_SET_LOCK and reading FCH_PLL_LOCKED. FCH_PLL_LOCKED is set to
“1” along with the high level of FCH_PLL_SET_LOCK and to “0” whenever the PLL falls out of
lock. So if the “1” remains in FCH_PLL_LOCKED, PLL is in sync.
The PLL controller’s operation is optimized for frequencies around 12. . . 13 MHz. If you use an
24. . . 26 MHz input clock, set the extra clock divider bit SM_CLK_RANGE in register SCI_MODE
to 1 before activating the PLL.
It’s recommended to change the PLL rate in small steps and wait for the PLL to stabilize after
each change. For diagnostic purposes, the PLL clock output (VCO) can be routed to an I/O pin
so it can be scanned with an oscilloscope.
FCH_PLL_RATE (bits 7:4) control PLL multiplication rate. PLL multiplier is (FCH_PLL_RATE
+ 1). When FCH_PLL_RATE is 0, the VCO is powered down and output clock is forced to be
input clock (same as if FCH_PLL_FORCE_PLL = 0).
Version: 1.22, 2014-12-19 74