Datasheet

VS1053b Datasheet
11 VS1053B REGISTERS
11.8 DAC Registers
DAC registers, prefix DAC_
Reg Type Reset Abbrev[bits] Description
0xC013 rw 0 FCTLL DAC frequency control, 16 LSbs
0xC014 rw 0 FCTLH DAC frequency control 4MSbs, PLL control
0xC015 rw 0 LEFT DAC left channel PCM value
0xC016 rw 0 RIGHT DAC right channel PCM value
0xC045 rw 0 VOL DAC hardware volume
The internal 20-bit register DAC_FCTL is calculated from DAC_FCTLH and DAC_FCTLL reg-
isters as follows: DAC_FCTL = (DAC_FCTLH & 15) × 65536 + DAC_FCTLL. Highest supported
value for DAC_FCTL is 0x80000.
If we define C = DAC_FCTL and X = XTALI in Hz, then the resulting samplerate f
s
of the asso-
ciated DAC SampleRate Converter is f
s
= C × X × 2
−27
.
Example:
If C = 0x80000 and X = 12.288 MHz then f
s
= 524288 × (12.288 × 10
6
) × 2
−27
= 48000 (Hz).
Note: FCTLH bits 13:4 are used for the PLL Controller. See Chapter 11.9 for details.
DAC_VOL bits
Name Bits Description
LEFT_FINE 15:12 Left channel gain +0.0 dB. . .+5.5 dB (0 to 11)
LEFT_COARSE 11:8 Left channel attenuation in -6 dB steps
RIGHT_FINE 7:4 Right channel volume +0.0 dB. . .+5.5 dB (0 to
11)
RIGHT_COARSE 3:0 Right channel attenuation in -6 dB steps
Normally DAC_VOL is handled by the firmware. DAC_VOL depends on SCI_VOL and the bass
and treble settings in SCI_BASS (and optionally SS_SWING bits in SCI_STATUS).
11.9 PLL Controller
The Phase-Locked Loop (PLL) controller is used to generate clock frequencies that are higher
than the incoming (crystal-based) clock frequency. The PLL output is used by the CPU core
and some peripherals.
Configurable features include:
• VCO Enable/Disable
• Select VCO or input clock to be output clock
• Route VCO frequency to output pin
Version: 1.22, 2014-12-19 73