Datasheet

VS1053b Datasheet
11 VS1053B REGISTERS
11.5 VS1053b Memory Map
X-memory
Address Description
0x0000..0x17ff System RAM
0x1800..0x187f User RAM
0x1880..0x197f Stack
0x1980..0x3fff System RAM
0x4000..0xbfff ROM 32k
0xc000..0xc0ff Peripherals
0xc100..0xffff ROM 15.75k
Y-memory
Address Description
0x0000..0x17ff System RAM
0x1800..0x187f User RAM
0x1880..0x197f Stack
0x1980..0x3fff System RAM
0x4000..0xdfff ROM 40k
0xe000..0xffff System RAM
I-memory
Address Description
0x0000..0x004f System RAM
0x0050..0x0fff User RAM
0x1000..0x1fff -
0x2000..0xffff ROM 56k
and banked
0xc000..0xffff ROM4 16k
11.6 SCI Hardware Registers
SCI registers described in Chapter 9.6 can be found here between 0xC000..0xC00F. In addition
to these registers, there is one in address 0xC010, called SCI_CHANGE.
SCI registers, prefix SCI_
Reg Type Reset Abbrev[bits] Description
0xC010 r 0 CHANGE[5:0] Last SCI access address
SCI_CHANGE bits
Name Bits Description
SCI_CH_WRITE 4 1 if last access was a write cycle
SCI_CH_ADDR 3:0 SCI address of last access
SCI_CHANGE contains the last SCI register that has been accessed through the SCI bus, as
well as whether the access was a read or write operation.
11.7 Serial Data Interface (SDI) Registers
Whenever two bytes have been written to the SDI bus, an interrupt is generated and the data
can be read as a 16-bit big-endian value from the SDI registers. The user can control the DREQ
pin as if it was a general-purpose output through its own register bit.
SDI registers, prefix SER_
Reg Type Reset Abbrev[bits] Description
0xC011 r 0 DATA Last received 2 bytes, big-endian
0xC012 w 0 DREQ[0] DREQ pin control
Version: 1.22, 2014-12-19 72