Datasheet

VS1053b Datasheet
10 OPERATION
will stay down for about 22000 clock cycles, which means an approximate 1.8 ms delay if
VS1053b is run at 12.288 MHz. After DREQ is up, you may continue playback as usual.
As opposed to all earlier VS10XX chips, it is not recommended to do a software reset between
songs. This way the user may be sure that even files with low samplerates or bitrates are played
right to their end.
10.4 Low Power Mode
If you need to keep the system running while not decoding data, but need to lower the power
consumption, you can use the following tricks.
• Select the 1.0× clock by writing 0x0000 to SCI_CLOCKF. This disables the PLL and saves
some power.
• Write a low non-zero value, such as 0x0010 to SCI_AUDATA. This will reduce the sam-
plerate and the number of audio interrupts required. Between audio interrupts the VSDSP
core will just wait for an interrupt, thus saving power.
• Turn off all audio post-processing (tone controls and EarSpeaker).
• If possible for the application, write 0xffff to SCI_VOL to disable the analog drivers.
To return from low-power mode, revert register values in reverse order.
Note: The low power mode consumes significantly more electricity than hardware reset.
10.5 Play and Decode
This is the normal operation mode of VS1053b. SDI data is decoded. Decoded samples are
converted to analog domain by the internal DAC. If no decodable data is found, SCI_HDAT0
and SCI_HDAT1 are set to 0.
When there is no input for decoding, VS1053b goes into idle mode (lower power consumption
than during decoding) and actively monitors the serial data input for valid data.
Version: 1.22, 2014-12-19 49