Datasheet

VS1053b Datasheet
10 OPERATION
10 Operation
10.1 Clocking
VS1053b operates on a single, nominally 12.288 MHz fundamental frequency master clock.
This clock can be generated by external circuitry (connected to pin XTALI) or by the inter-
nal clock crystal interface (pins XTALI and XTALO). This clock is used by the analog parts
and determines the highest available samplerate. With 12.288 MHz clock all samplerates upto
48000 Hz are available.
VS1053b can also use 24..26 MHz clocks when SM_CLK_RANGE in the SCI_MODE register is
set to 1. The system clock is then divided by 2 at the clock input and the chip gets a 12..13 MHz
input clock.
10.2 Hardware Reset
When the XRESET -signal is driven low, VS1053b is reset and all the control registers and
internal states are set to the initial values. XRESET-signal is asynchronous to any external
clock. The reset mode doubles as a full-powerdown mode, where both digital and analog parts
of VS1053b are in minimum power consumption stage, and where clocks are stopped. Also
XTALO is grounded.
When XRESET is asseted, all output pins go to their default states. All input pins will go to
high-impedance state (to input state), except SO, which is still controlled by the XCS.
After a hardware reset (or at power-up) DREQ will stay down for around 22000 clock cycles,
which means an approximate 1.8 ms delay if VS1053b is run at 12.288 MHz. After this the
user should set such basic software registers as SCI_MODE, SCI_BASS, SCI_CLOCKF, and
SCI_VOL before starting decoding. See section 9.6 for details.
If the input clock is 24..26 MHz, SM_CLK_RANGE should be set as soon as possible after a
chip reset without waiting for DREQ.
Internal clock can be multiplied with a PLL. Supported multipliers through the SCI_CLOCKF
register are 1.0 × . . . 5.0× the input clock. Reset value for Internal Clock Multiplier is 1.0×. If
typical values are wanted, the Internal Clock Multiplier needs to be set to 3.5× after reset. Wait
until DREQ rises, then write value 0x9800 to SCI_CLOCKF (register 3). See section 9.6.4 for
details.
10.3 Software Reset
In some cases the decoder software has to be reset. This is done by activating bit SM_RESET
in register SCI_MODE (Chapter 9.6.1). Then wait for at least 2 µs, then look at DREQ. DREQ
Version: 1.22, 2014-12-19 48