Datasheet

VS1053b Datasheet
9 FUNCTIONAL DESCRIPTION
9.6.4 SCI_CLOCKF (RW)
The external clock multiplier SCI register SCI_CLOCKF, which has changed slightly since
VS1003 and VS1033, is presented in the table below.
SCI_CLOCKF bits
Name Bits Description
SC_MULT 15:13 Clock multiplier
SC_ADD 12:11 Allowed multiplier addition
SC_FREQ 10: 0 Clock frequency
SC_MULT activates the built-in clock multiplier. This will multiply XTALI to create a higher CLKI.
When the multiplier is changed by more than 0.5×, the chip runs at 1.0× clock for a few hundres
clock cycles. The values are as follows:
SC_MULT MASK CLKI
0 0x0000 XTALI
1 0x2000 XTALI×2.0
2 0x4000 XTALI×2.5
3 0x6000 XTALI×3.0
4 0x8000 XTALI×3.5
5 0xa000 XTALI×4.0
6 0xc000 XTALI×4.5
7 0xe000 XTALI×5.0
SC_ADD tells how much the decoder firmware is allowed to add to the multiplier specified by
SC_MULT if more cycles are temporarily needed to decode a WMA or AAC stream. The values
are:
SC_ADD MASK Multiplier addition
0 0x0000 No modification is allowed
1 0x0800 XTALI×1.0
2 0x1000 XTALI×1.5
3 0x1800 XTALI×2.0
If SC_FREQ is non-zero, it tells that the input clock XTALI is running at something else than
12.288 MHz. XTALI is set in 4 kHz steps. The formula for calculating the correct value for this
register is
XT ALI−8000000
4000
(XTALI is in Hz).
Note: because maximum samplerate is
XT ALI
256
, all samplerates are not available if XTALI <
12.288 MHz.
Note: Automatic clock change can only happen when decoding WMA and AAC files. Automatic
clock change is done one 0.5× at a time. This does not cause a drop to 1.0× clock and you can
use the same SCI and SDI clock throughout the file.
Example: If SCI_CLOCKF is 0x8BE8, SC_MULT = 4, SC_ADD = 1 and SC_FREQ = 0x3E8 = 1000.
This means that XTALI = 1000 × 4000 + 8000000 = 12 MHz. The clock multiplier is set to
3.5×XTALI = 42 MHz, and the maximum allowed multiplier that the firmware may automatically
choose to use is (3.5 + 1.0)×XTALI = 54 MHz.
Version: 1.22, 2014-12-19 42