Datasheet

VS1053b Datasheet
9 FUNCTIONAL DESCRIPTION
Bits SM_EARSPEAKER_LO and SM_EARSPEAKER_HI control the EarSpeaker spatial pro-
cessing. If both are 0, the processing is not active. Other combinations activate the processing
and select 3 different effect levels: LO = 1, HI = 0 selects minimal, LO = 0, HI = 1 selects nor-
mal, and LO = 1, HI = 1 selects extreme. EarSpeaker takes approximately 12 MIPS at 44.1 kHz
samplerate.
If SM_TESTS is set, SDI tests are allowed. For more details on SDI tests, look at Chapter 10.12.
SM_STREAM activates VS1053b’s stream mode. In this mode, data should be sent with as
even intervals as possible and preferable in blocks of less than 512 bytes, and VS1053b makes
every attempt to keep its input buffer half full by changing its playback speed upto 5%. For best
quality sound, the average speed error should be within 0.5%, the bitrate should not exceed
160 kbit/s and VBR should not be used. For details, see Application Notes for VS10XX. This
mode only works with MP3 and WAV files.
SM_DACT defines the active edge of data clock for SDI. When ’0’, data is read at the rising
edge, when ’1’, data is read at the falling edge.
When SM_SDIORD is clear, bytes on SDI are sent MSb first. By setting SM_SDIORD, the user
may reverse the bit order for SDI, i.e. bit 0 is received first and bit 7 last. Bytes are, however,
still sent in the default order. This register bit has no effect on the SCI bus.
Setting SM_SDISHARE makes SCI and SDI share the same chip select, as explained in Chap-
ter 7.1, if also SM_SDINEW is set.
Setting SM_SDINEW will activate VS1002 native serial modes as described in Chapters 7.1.1 and 7.3.1.
Note, that this bit is set as a default when VS1053b is started up.
By activating SM_ADPCM and SM_RESET at the same time, the user will activate IMA ADPCM
recording mode (see section 10.8).
SM_LINE_IN is used to select the left-channel input for ADPCM recording. If ’0’, differential
microphone input pins MICP and MICN are used; if ’1’, line-level MICP/LINEIN1 pin is used.
SM_CLK_RANGE activates a clock divider in the XTAL input. When SM_CLK_RANGE is set,
the clock is divided by 2 at the input. From the chip’s point of view e.g. 24 MHz becomes
12 MHz. SM_CLK_RANGE should be set as soon as possible after a chip reset.
Version: 1.22, 2014-12-19 39