Datasheet

VS1053b Datasheet
9 FUNCTIONAL DESCRIPTION
9.2 Data Flow of VS1053b
Volume
control
Audio
FIFO
S.rate.conv.
and DAC
R
Bitstream
FIFO
SDI
L
SCI_VOL
SM_ADPCM=0
2048 stereo
samples
Bass
enhancer
SB_AMPLITUDE=0
SB_AMPLITUDE!=0
AIADDR = 0
AIADDR != 0
User
Application
ST_AMPLITUDE=0
ST_AMPLITUDE!=0
Ear
Speaker
MP3 MP2 MP1
WAV ADPCM
WMA AAC
MIDI Vorbis
Treble
control
Figure 16: Data flow of VS1053b.
First, depending on the audio data, and provided ADPCM encoding mode is not set, Ogg
Vorbis, PCM WAV or IMA ADPCM WAV is received and decoded from the SDI bus.
After decoding, if SCI_AIADDR is non-zero, application code is executed from the address
pointed to by that register. For more details, see Application Notes for VS10XX.
Then data may be sent to the Bass Enhancer and Treble Control depending on the SCI_BASS
register.
Next, headphone processing is performed, if the EarSpeaker spatial processing is active.
After that the data to the Audio FIFO, which holds the data until it is read by the Audio interrupt
and fed to the samplerate converter and DACs. The size of the audio FIFO is 2048 stereo
(2×16-bit) samples, or 8 KiB.
The samplerate converter upsamples all different samplerates to XTALI/2, or 128 times the
highest usable samplerate with 18-bit precision. Volume control is performed in the upsampled
domain. New volume settings are loaded only when the upsampled signal crosses the zero
point (or after a timeout). This zero-crossing detection almost completely removes all audible
noise that occurs when volume is suddenly changed.
The samplerate conversion to a common samplerate removes the need for complex PLL-based
clocking schemes and allows almost unlimited sample rate accuracy with one fixed input clock
frequency. With a 12.288 MHz clock, the DA converter operates at 128 × 48 kHz, i.e. 6.144
MHz, and creates a stereo in-phase analog signal. The oversampled output is low-pass filtered
by an on-chip analog filter. This signal is then forwarded to the earphone amplifier.
Version: 1.22, 2014-12-19 34