Datasheet

VS1053b Datasheet
7 SPI BUSES
7.3.2 SDI Timing Diagram in VS10xx Native Modes (New Mode)
SCK
SI
tXCSS
tXCSHtWL tWH
tH
tSU
tXCS
xDCS
D7 D6 D5 D4
D3
D2
D1
D0
Figure 6: SDI timing diagram
Figure 6 presents SDI bus timing.
Symbol Min Max Unit
tXCSS 5 ns
tSU 0 ns
tH 2 CLKI cycles
tWL 2 CLKI cycles
tWH 2 CLKI cycles
tXCSH 1 CLKI cycles
tXCS 0 CLKI cycles
Note: xDCS is not required to go high between bytes, so tXCS is 0.
Note: Although the timing is derived from the internal clock CLKI, the system always starts up in
1.0× mode, thus CLKI=XTALI. After you have configured a higher clock through SCI_CLOCKF
and waited for DREQ to rise, you can use a higher SPI speed as well.
Version: 1.22, 2014-12-19 18