Datasheet

VS1053b Datasheet
7 SPI BUSES
7.3 Serial Protocol for Serial Data Interface (SPI / SDI)
The serial data interface operates in slave mode so DCLK signal must be generated by an
external circuit.
Data (SDATA signal) can be clocked in at either the rising or falling edge of DCLK (Chapter 9.6).
VS1053b assumes its data input to be byte-sychronized. SDI bytes may be transmitted either
MSb or LSb first, depending of register SCI_MODE bit SM_SDIORD (Chapter 9.6.1).
The firmware is able to accept the maximum bitrate the SDI supports.
7.3.1 SDI in VS10xx Native Modes (New Mode, recommended)
DCLK
D7 D6 D5 D4 D3 D1D2 D0SDATA
XDCS
Figure 4: SDI in VS10xx Native Mode, single-byte transfer
In VS10xx native modes (SM_NEWMODE is 1), byte synchronization is achieved by XDCS, as
shown in Figure 4. The state of XDCS may not change while a data byte transfer is in progress.
XDCS does not need to be deactivated and reactivated for every byte transfer, as shown in
Figure 5. However, to maintain data synchronization even if there are occasional clock glitches,
it is recommended to deactivate and reactivate XDCS every now and then, for example after
each 32 bytes of data.
Note that when sending data through SDI you have to check the Data Request Pin DREQ at
least after every 32 bytes (Chapter 7.2).
DCLK
SDATA D7 D6 D5 D4 D3 D1D2 D0 D7 D6 D5
...
D3 D1D2 D0
Byte XByte 1 Byte 2
...
XDCS
Figure 5: SDI in VS10xx Native Mode, multi-byte transfer, X ≥ 1
If SM_SDISHARE is 1, the XDCS signal is internally generated by inverting the XCS input.
Version: 1.22, 2014-12-19 17