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VS1053b Datasheet

VS1053b -

Ogg Vorbis/MP3/AAC/WMA/FLAC/

MIDI AUDIO CODEC CIRCUIT

Features

• Decodes

Ogg Vorbis;

MP3 = MPEG 1 & 2 audio layer III (CBR

+VBR +ABR);

MP1/MP2 = layers I & II optional;

MPEG4 / 2 AAC-LC(+PNS),

HE-AAC v2 (Level 3) (SBR + PS);

WMA 4.0/4.1/7/8/9 all proﬁles (5-384 kbps);

General MIDI 1 / SP-MIDI format 0 ﬁles;

FLAC with software plugin;

WAV (PCM + IMA ADPCM)

• Encodes Ogg Vorbis w/ software plugin

• Encodes stereo IMA ADPCM / PCM

• Streaming support for MP3 and WAV

• EarSpeaker Spatial Processing

• Bass and treble controls

• Operates with a single 12..13 MHz clock

• Can also be used with a 24..26 MHz clock

• Internal PLL clock multiplier

• Low-power operation

• High-quality on-chip stereo DAC with no

phase error between channels

• Zero-cross detection for smooth volume

change

• Stereo earphone driver capable of driv-

ing a 30 Ω load

• Quiet power-on and power-off

• I2S output interface for external DAC

• Separate voltages for analog, digital, I/O

• On-chip RAM for user code and data

• Serial control and data interfaces

• Can be used as a slave co-processor

• SPI ﬂash boot for special applications

• UART for debugging purposes

• New functions may be added with soft-

ware and upto 8 GPIO pins

• Lead-free RoHS-compliant package

Description

VS1053b is an Ogg Vorbis/MP3/AAC/WMA/

FLAC/WAVMIDI audio decoder as well as an

PCM/IMA ADPCM/Ogg Vorbis encoder on a

single chip. It contains a high-performance,

proprietary low-power DSP processor core

VS_DSP

, data memory, 16 KiB instruction

RAM and 0.5+ KiB data RAM for user appli-

cations running simultaneously with any built-

in decoder, serial control and input data in-

terfaces, upto 8 general purpose I/O pins, an

UART, as well as a high-quality variable-sample-

rate stereo ADC (mic, line, line + mic or 2×line)

and stereo DAC, followed by an earphone am-

pliﬁer and a common voltage buffer.

VS1053b receives its input bitstream through

a serial input bus, which it listens to as a

system slave. The input stream is decoded

and passed through a digital volume control

to an 18-bit oversampling, multi-bit, sigma-

delta DAC. The decoding is controlled via a

serial control bus. In addition to the basic de-

coding, it is possible to add application spe-

ciﬁc features, like DSP effects, to the user

RAM memory.

Optional factory-programmable unique chip

ID provides basis for digital rights manage-

ment or unit identiﬁcation features.

Version: 1.22, 2014-12-19 1

Summary of content (89 pages)

PAGE 1
VS1053b Datasheet VS1053b Ogg Vorbis/MP3/AAC/WMA/FLAC/ MIDI AUDIO CODEC CIRCUIT Features • Decodes Ogg Vorbis; MP3 = MPEG 1 & 2 audio layer III (CBR +VBR +ABR); MP1/MP2 = layers I & II optional; MPEG4 / 2 AAC-LC(+PNS), HE-AAC v2 (Level 3) (SBR + PS); WMA 4.0/4.
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VS1053b Datasheet CONTENTS Contents VS1053 1 Table of Contents 2 List of Figures 5 1 Licenses 6 2 Disclaimer 6 3 Definitions 6 4 Characteristics & Specifications 4.1 Absolute Maximum Ratings . . . . . . . . . 4.2 Recommended Operating Conditions . . . . 4.3 Analog Characteristics . . . . . . . . . . . . 4.4 Power Consumption . . . . . . . . . . . . . 4.5 Digital Characteristics . . . . . . . . . . . . . 4.6 Switching Characteristics - Boot Initialization . . . . . .
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VS1053b Datasheet 8.3 8.4 8.5 8.6 8.7 8.8 8.9 Supported MP1 (MPEG layer I) Formats . . . . . . . . . . . . . . . Supported Ogg Vorbis Formats . . . . . . . . . . . . . . . . . . . . Supported AAC (ISO/IEC 13818-7 and ISO/IEC 14496-3) Formats Supported WMA Formats . . . . . . . . . . . . . . . . . . . . . . . Supported FLAC Formats . . . . . . . . . . . . . . . . . . . . . . . Supported RIFF WAV Formats . . . . . . . . . . . . . . . . . . . . . Supported MIDI Formats . . . . . . . . . . . . . . . . . . . .
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VS1053b Datasheet 10.11 Extra Parameters . . . . . . . . . . . . 10.11.1 Common Parameters . . . . 10.11.2 WMA . . . . . . . . . . . . . 10.11.3 AAC . . . . . . . . . . . . . 10.11.4 Midi . . . . . . . . . . . . . . 10.11.5 Ogg Vorbis . . . . . . . . . . 10.12 SDI Tests . . . . . . . . . . . . . . . . 10.12.1 Old Sine Test . . . . . . . . 10.12.2 New Sine and Sweep Tests 10.12.3 Pin Test . . . . . . . . . . . 10.12.4 SCI Test . . . . . . . . . . . 10.12.5 Memory Test . . . . . . . . . . . . . . . . . . . .
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VS1053b Datasheet LIST OF FIGURES List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Pin configuration, LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . VS1053b in LQFP-48 packaging. . . . . . . . . . . . . . . . . . . . . . . . . Typical connection diagram using LQFP-48. . . . . . . . . . . . . . . . . . . SDI in VS10xx Native Mode, single-byte transfer . . . . . . . . . . . . . . . SDI in VS10xx Native Mode, multi-byte transfer, X ≥ 1 . . . . . . . . . . . .
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VS1053b Datasheet 1 3 DEFINITIONS Licenses MPEG Layer-3 audio decoding technology licensed from Fraunhofer IIS and Thomson. Note: If you enable Layer I and Layer II decoding, you are liable for any patent issues that may arise from using these formats. Joint licensing of MPEG 1.0 / 2.0 Layer III does not cover all patents pertaining to layers I and II. VS1053b contains WMA decoding technology from Microsoft.
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VS1053b Datasheet 4 4 4.1 Characteristics & Specifications Absolute Maximum Ratings Parameter Analog Positive Supply Digital Positive Supply I/O Positive Supply Current at Any Non-Power Pin1 Voltage at Any Digital Input Operating Temperature Storage Temperature 1 2 CHARACTERISTICS & SPECIFICATIONS Symbol AVDD CVDD IOVDD Min -0.3 -0.3 -0.3 -0.3 -30 -65 Max 3.6 1.85 3.6 ±50 IOVDD+0.32 +85 +150 Unit V V V mA V ◦C ◦C Higher current can cause latch-up. Must not exceed 3.6 V 4.
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VS1053b Datasheet 4 4.3 CHARACTERISTICS & SPECIFICATIONS Analog Characteristics Unless otherwise noted: AVDD=3.3V, CVDD=1.8V, IOVDD=2.8V, REF=1.65V, TA=-30..+85◦ C, XTALI=12..13MHz, Internal Clock Multiplier 3.5×. DAC tested with 1307.894 Hz full-scale output sinewave, measurement bandwidth 20..20000 Hz, analog output load: LEFT to GBUF 30 Ω, RIGHT to GBUF 30 Ω. Microphone test amplitude 48 mVpp, fs =1 kHz, Line input test amplitude 2.52 Vpp, fs =1 kHz.
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VS1053b Datasheet 4 4.4 CHARACTERISTICS & SPECIFICATIONS Power Consumption Tested with an Ogg Vorbis 128 kbps sample and generated sine. Output at full volume. Internal clock multiplier 3.0×. TA=+25◦ C. Parameter Power Supply Consumption AVDD, Reset Power Supply Consumption CVDD = 1.8V, Reset Power Supply Consumption AVDD, sine test, 30 Ω + GBUF Power Supply Consumption CVDD = 1.
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VS1053b Datasheet 5 5 PACKAGES AND PIN DESCRIPTIONS Packages and Pin Descriptions 5.1 Packages LPQFP-48 is a lead (Pb) free and also RoHS compliant package. RoHS is a short name of Directive 2002/95/EC on the restriction of the use of certain hazardous substances in electrical and electronic equipment. 5.1.1 LQFP-48 48 1 Figure 1: Pin configuration, LQFP-48. LQFP-48 package dimensions are at http://www.vlsi.fi/ . Figure 2: VS1053b in LQFP-48 packaging. Version: 1.
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VS1053b Datasheet 5 Pad Name MICP / LINE1 MICN XRESET DGND0 CVDD0 IOVDD0 CVDD1 DREQ GPIO2 / DCLK1 GPIO3 / SDATA1 GPIO6 / I2S_SCLK3 GPIO7 / I2S_SDATA3 XDCS / BSYNC1 IOVDD1 VCO DGND1 XTALO XTALI IOVDD2 DGND2 DGND3 DGND4 XCS CVDD2 GPIO5 / I2S_MCLK3 RX TX SCLK SI SO CVDD3 XTEST GPIO0 GPIO1 GND GPIO4 I2S_LROUT3 AGND0 AVDD0 RIGHT AGND1 AGND2 GBUF AVDD1 RCAP AVDD2 LEFT AGND3 LINE2 / PACKAGES AND PIN DESCRIPTIONS LQFP Pin 1 2 3 4 5 6 7 8 9 10 11 12 Pin Type AI AI DI DGND CPWR IOPWR CPWR DO DIO DIO DIO DIO Fun
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VS1053b Datasheet 5 PACKAGES AND PIN DESCRIPTIONS 1 First pin function is active in New Mode, latter in Compatibility Mode. 2 If GPIO0 is high, SPI Boot is tried. See Chapter 10.9 for details. 3 If GPIO0 is low and GPIO1 is high, Real-Time MIDI mode is entered. See Chapter 10.10 for details. 4 If I2S_CF_ENA is ’0’ the pins are used for GPIO. See Chapter 11.14 for details.
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VS1053b Datasheet 6 6 CONNECTION DIAGRAM, LQFP-48 Connection Diagram, LQFP-48 Figure 3: Typical connection diagram using LQFP-48. Figure 3 shows a typical connection diagram for VS1053. Figure Note 1: Connect either Microphone In or Line In, but not both at the same time. Note: This connection assumes SM_SDINEW is active (see Chapter 9.6.1). If also SM_SDISHARE is used, xDCS should be tied low or high (see Chapter 7.1.1). Version: 1.
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VS1053b Datasheet 6 CONNECTION DIAGRAM, LQFP-48 The common buffer GBUF can be used for common voltage (1.23 V) for earphones. This will eliminate the need for large isolation capacitors on line outputs, and thus the audio output pins from VS1053b may be connected directly to the earphone connector. GBUF must NOT be connected to ground under any circumstances. If GBUF is not used, LEFT and RIGHT must be provided with coupling capacitors.
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VS1053b Datasheet 7 7 SPI BUSES SPI Buses The SPI Bus - which was originally used in some Motorola devices - has been used for both VS1053b’s Serial Data Interface SDI (Chapters 7.3 and 9.4) and Serial Control Interface SCI (Chapters 7.4 and 9.5). 7.1 SPI Bus Pin Descriptions 7.1.1 VS10xx Native Modes (New Mode, recommended) These modes are active on VS1053b when SM_SDINEW is set to 1 (default at startup).
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VS1053b Datasheet 7.2 7 SPI BUSES Data Request Pin DREQ The DREQ pin/signal is used to signal if VS1053b’s 2048-byte FIFO is capable of receiving data. If DREQ is high, VS1053b can take at least 32 bytes of SDI data or one SCI command. DREQ is turned low when the stream buffer is too full and for the duration of an SCI command.
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VS1053b Datasheet 7.3 7 SPI BUSES Serial Protocol for Serial Data Interface (SPI / SDI) The serial data interface operates in slave mode so DCLK signal must be generated by an external circuit. Data (SDATA signal) can be clocked in at either the rising or falling edge of DCLK (Chapter 9.6). VS1053b assumes its data input to be byte-sychronized. SDI bytes may be transmitted either MSb or LSb first, depending of register SCI_MODE bit SM_SDIORD (Chapter 9.6.1).
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VS1053b Datasheet 7.3.2 7 SPI BUSES SDI Timing Diagram in VS10xx Native Modes (New Mode) tWL tXCSS tWH tXCSH xDCS D7 D6 D5 D4 D3 D2 tXCS D1 D0 SCK SI tH tSU Figure 6: SDI timing diagram Figure 6 presents SDI bus timing. Symbol tXCSS tSU tH tWL tWH tXCSH tXCS Min 5 0 2 2 2 1 0 Max Unit ns ns CLKI cycles CLKI cycles CLKI cycles CLKI cycles CLKI cycles Note: xDCS is not required to go high between bytes, so tXCS is 0.
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VS1053b Datasheet 7.3.3 7 SPI BUSES SDI in VS1001 Compatibility Mode (deprecated, do not use in new designs) BSYNC SDATA D7 D6 D5 D4 D3 D2 D1 D0 DCLK Figure 7: SDI in VS1001 Mode - one byte transfer. Do not use in new designs! When VS1053b is running in VS1001 compatibility mode, a BSYNC signal must be generated to ensure correct bit-alignment of the input bitstream, as shown in Figures 7 and 8.
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VS1053b Datasheet 7.4 7 SPI BUSES Serial Protocol for Serial Command Interface (SPI / SCI) The serial bus protocol for the Serial Command Interface SCI (Chapter 9.5) consists of an instruction byte, address byte and one 16-bit data word. Each read or write operation can read or write a single register. Data bits are read at the rising edge, so the user should update data at the falling edge. Bytes are always send MSb first.
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VS1053b Datasheet 7.4.2 7 SPI BUSES SCI Write XCS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 0 0 0 0 0 1 0 0 0 0 30 31 SCK 3 SI instruction (write) SO 0 0 0 0 0 0 2 1 15 14 0 0 0 0 0 X data out address 0 1 0 0 0 0 0 0 0 0 0 0 X 0 execution DREQ Figure 10: SCI word write VS1053b registers are written from using the following sequence, as shown in Figure 10. First, XCS line is pulled low to select the device.
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VS1053b Datasheet 7 SPI BUSES bringing XCS up after sending the last bit of a data word, the next data word is sent immediately. After the last data word, XCS is driven high as with a single word write. After the last bit of a word has been sent, DREQ is driven low for the duration of the register update, marked “execution” in the figure. The time varies depending on the register and its contents (see table in Chapter 9.6 for details).
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VS1053b Datasheet 7.5 7.5.1 7 SPI BUSES SPI Examples with SM_SDINEW and SM_SDISHARED set Two SCI Writes SCI Write 1 SCI Write 2 XCS 0 1 2 3 30 31 1 0 32 33 61 62 63 2 1 0 SCK SI 0 0 0 X 0 0 X 0 DREQ up before finishing next SCI write DREQ Figure 13: Two SCI operations Figure 13 shows two consecutive SCI operations. Note that xCS must be raised to inactive state between the writes. Also DREQ must be respected as shown in the figure. 7.5.
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VS1053b Datasheet 7.5.3 7 SPI BUSES SCI Operation in Middle of Two SDI Bytes SDI Byte SDI Byte SCI Operation XCS 0 7 1 8 9 39 40 41 7 6 46 47 1 0 SCK 7 6 5 1 0 0 SI 5 X 0 DREQ high before end of next transfer DREQ Figure 15: Two SDI bytes separated by an SCI operation Figure 15 shows how an SCI operation is embedded in between SDI operations. xCS edges are used to synchronize both SDI and SCI. Remember to respect DREQ as shown in the figure. Version: 1.
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VS1053b Datasheet 8 8 Supported Audio Decoder Formats Mark + ? - 8.1 SUPPORTED AUDIO DECODER FORMATS Conventions Description Format is supported Format is supported but not thoroughly tested Format exists but is not supported Format doesn’t exist Supported MP3 (MPEG layer III) Formats MPEG 1.
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VS1053b Datasheet 8 8.2 SUPPORTED AUDIO DECODER FORMATS Supported MP2 (MPEG layer II) Formats Note: Layer I / II decoding must be specifically enabled from register SCI_MODE. MPEG 1.
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VS1053b Datasheet 8 8.5 SUPPORTED AUDIO DECODER FORMATS Supported AAC (ISO/IEC 13818-7 and ISO/IEC 14496-3) Formats VS1053b decodes MPEG2-AAC-LC-2.0.0.0 and MPEG4-AAC-LC-2.0.0.0 streams, i.e. the low complexity profile with maximum of two channels can be decoded. If a stream contains more than one element and/or element type, you can select which one to decode from the 16 singlechannel, 16 channel-pair, and 16 low-frequency elements. The default is to select the first one that appears in the stream.
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VS1053b Datasheet 8 SUPPORTED AUDIO DECODER FORMATS mdat atom last in the file, and thus suitable for web servers’ audio streaming. You can use this kind of tool to process files for VS1053b too. For example mp4creator -optimize file.mp4.
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VS1053b Datasheet 8 8.6 SUPPORTED AUDIO DECODER FORMATS Supported WMA Formats Windows Media Audio codec versions 2, 7, 8, and 9 are supported. All WMA profiles (L1, L2, and L3) are supported. Previously streams were separated into Classes 1, 2a, 2b, and 3. The decoder has passed Microsoft’s conformance testing program. Windows Media Audio Professional is a different codec and is not supported. WMA 4.0 / 4.
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VS1053b Datasheet 8 8.7 SUPPORTED AUDIO DECODER FORMATS Supported FLAC Formats Upto 48 kHz and 24-bit FLAC files are supported with the VS1053b Patches w/ FLAC Decoder plugin that is available at http://www.vlsi.fi/en/support/software/vs10xxplugins.html . Read the accompanying documentation of the plugin for details. 8.8 Supported RIFF WAV Formats The most common RIFF WAV subformats are supported, with 1 or 2 audio channels.
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VS1053b Datasheet 8 8.9 SUPPORTED AUDIO DECODER FORMATS Supported MIDI Formats General MIDI and SP-MIDI format 0 files are played. Format 1 and 2 files must be converted to format 0 by the user. The maximum polyphony is 64, the maximum sustained polyphony is 40.
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VS1053b Datasheet 8 1 Acoustic Grand Piano 2 Bright Acoustic Piano 3 Electric Grand Piano 4 Honky-tonk Piano 5 Electric Piano 1 6 Electric Piano 2 7 Harpsichord 8 Clavi 9 Celesta 10 Glockenspiel 11 Music Box 12 Vibraphone 13 Marimba 14 Xylophone 15 Tubular Bells 16 Dulcimer 17 Drawbar Organ 18 Percussive Organ 19 Rock Organ 20 Church Organ 21 Reed Organ 22 Accordion 23 Harmonica 24 Tango Accordion 25 Acoustic Guitar (nylon) 26 Acoustic Guitar (steel) 27 Electric Guitar (jazz) 28 Electric Guitar (clean) 29
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VS1053b Datasheet 9 9 9.1 FUNCTIONAL DESCRIPTION Functional Description Main Features VS1053b is based on a proprietary digital signal processor, VS_DSP. It contains all the code and data memory needed for Ogg Vorbis, MP3, AAC, WMA and WAV PCM + ADPCM audio decoding and a MIDI synthesizer, together with serial interfaces, a multirate stereo audio DAC and analog output amplifiers and filters.
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VS1053b Datasheet 9 9.2 FUNCTIONAL DESCRIPTION Data Flow of VS1053b SDI Bitstream FIFO MP3 MP2 MP1 WAV ADPCM WMA AAC MIDI Vorbis SM_ADPCM=0 SB_AMPLITUDE=0 AIADDR = 0 Bass enhancer User Application Treble control SB_AMPLITUDE!=0 AIADDR != 0 Audio FIFO 2048 stereo samples ST_AMPLITUDE=0 Ear Speaker ST_AMPLITUDE!=0 L S.rate.conv. R and DAC Volume SCI_VOL control Figure 16: Data flow of VS1053b.
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VS1053b Datasheet 9 9.3 FUNCTIONAL DESCRIPTION EarSpeaker Spatial Processing While listening to headphones the sound has a tendency to be localized inside the head. The sound field becomes flat and lacking the sensation of dimensions. This is an unnatural, awkward and sometimes even disturbing situation. This phenomenon is often referred in literature as ‘lateralization’, meaning ’in-the-head’ localization. Long-term listening to lateralized sound may lead to listening fatigue.
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VS1053b Datasheet 9 FUNCTIONAL DESCRIPTION • normal: Suited for listening to normal musical scores with headphones, moves sound source further away than minimal. • extreme: Suited for old or ’dry’ recordings, or if the audio to be played is artificial, for example generated MIDI. 9.4 Serial Data Interface (SDI) The serial data interface is meant for transferring compressed data for the different decoders of VS1053b.
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VS1053b Datasheet 9 9.6 FUNCTIONAL DESCRIPTION SCI Registers VS1053b sets DREQ low when it detects an SCI operation (this delay is 16 to 40 CLKI cycles depending on whether an interrupt service routine is active) and restores it when it has processed the operation. The duration depends on the operation. If DREQ is low when an SCI operation is performed, it also stays low after SCI operation processing.
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VS1053b Datasheet 9 9.6.1 FUNCTIONAL DESCRIPTION SCI_MODE (RW) SCI_MODE is used to control the operation of VS1053b and defaults to 0x4800 (SM_SDINEW set).
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VS1053b Datasheet 9 FUNCTIONAL DESCRIPTION Bits SM_EARSPEAKER_LO and SM_EARSPEAKER_HI control the EarSpeaker spatial processing. If both are 0, the processing is not active. Other combinations activate the processing and select 3 different effect levels: LO = 1, HI = 0 selects minimal, LO = 0, HI = 1 selects normal, and LO = 1, HI = 1 selects extreme. EarSpeaker takes approximately 12 MIPS at 44.1 kHz samplerate. If SM_TESTS is set, SDI tests are allowed. For more details on SDI tests, look at Chapter 10.
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VS1053b Datasheet 9 9.6.2 FUNCTIONAL DESCRIPTION SCI_STATUS (RW) SCI_STATUS contains information on the current status of VS1053b. It also controls some low-level things that the user does not usually have to care about. Name SS_DO_NOT_JUMP SS_SWING SS_VCM_OVERLOAD SS_VCM_DISABLE SS_VER SS_APDOWN2 SS_APDOWN1 SS_AD_CLOCK SS_REFERENCE_SEL Bits 15 14:12 11 10 9:8 7:4 3 2 1 0 Description Header in decode, do not fast forward/rewind Set swing to +0 dB, +0.5 dB, .., or +3.
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VS1053b Datasheet 9 9.6.3 FUNCTIONAL DESCRIPTION SCI_BASS (RW) Name ST_AMPLITUDE ST_FREQLIMIT SB_AMPLITUDE SB_FREQLIMIT Bits 15:12 11:8 7:4 3:0 Description Treble Control in 1.5 dB steps (-8..7, 0 = off) Lower limit frequency in 1000 Hz steps (1..15) Bass Enhancement in 1 dB steps (0..15, 0 = off) Lower limit frequency in 10 Hz steps (2..15) The Bass Enhancer VSBE is a powerful bass boosting DSP algorithm, which tries to take the most out of the users earphones without causing clipping.
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VS1053b Datasheet 9 9.6.4 FUNCTIONAL DESCRIPTION SCI_CLOCKF (RW) The external clock multiplier SCI register SCI_CLOCKF, which has changed slightly since VS1003 and VS1033, is presented in the table below. Name SC_MULT SC_ADD SC_FREQ SCI_CLOCKF bits Bits Description 15:13 Clock multiplier 12:11 Allowed multiplier addition 10: 0 Clock frequency SC_MULT activates the built-in clock multiplier. This will multiply XTALI to create a higher CLKI. When the multiplier is changed by more than 0.
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VS1053b Datasheet 9 9.6.5 FUNCTIONAL DESCRIPTION SCI_DECODE_TIME (RW) When decoding correct data, current decoded time is shown in this register in full seconds. The user may change the value of this register. In that case the new value should be written twice to make absolutely certain that the change is not overwritten by the firmware. A write to SCI_DECODE_TIME also resets the byteRate calculation. SCI_DECODE_TIME is reset at every hardware and software reset.
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VS1053b Datasheet 9 9.6.8 FUNCTIONAL DESCRIPTION SCI_WRAMADDR (W) SCI_WRAMADDR is used to set the program address for following SCI_WRAM writes/reads. Use an address offset from the following table to access X, Y, I or peripheral memory. WRAMADDR Start. . . End 0x1800. . . 0x18XX 0x5800. . . 0x58XX 0x8040. . . 0x84FF 0xC000. . . 0xFFFF Dest. addr. Start. . . End 0x1800. . . 0x18XX 0x1800. . . 0x18XX 0x0040. . . 0x04FF 0xC000. . .
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VS1053b Datasheet 9 FUNCTIONAL DESCRIPTION For MP3 files, SCI_HDAT1 is between 0xFFE0 and 0xFFFF.
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VS1053b Datasheet 9 FUNCTIONAL DESCRIPTION The “bitrate” field in HDAT0 is read according to the following table. Notice that for variable bitrate stream the value changes constantly.
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VS1053b Datasheet 9 9.6.10 FUNCTIONAL DESCRIPTION SCI_AIADDR (RW) SCI_AIADDR indicates the start address of the application code written earlier with SCI_WRAMADDR and SCI_WRAM registers. If no application code is used, this register should not be initialized, or it should be initialized to zero. For more details, see Application Notes for VS10XX. Note: Reading AIADDR is not recommended. It can cause samplerate to be set to a very low value. 9.6.
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VS1053b Datasheet 10 10.1 10 OPERATION Operation Clocking VS1053b operates on a single, nominally 12.288 MHz fundamental frequency master clock. This clock can be generated by external circuitry (connected to pin XTALI) or by the internal clock crystal interface (pins XTALI and XTALO). This clock is used by the analog parts and determines the highest available samplerate. With 12.288 MHz clock all samplerates upto 48000 Hz are available. VS1053b can also use 24..
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VS1053b Datasheet 10 OPERATION will stay down for about 22000 clock cycles, which means an approximate 1.8 ms delay if VS1053b is run at 12.288 MHz. After DREQ is up, you may continue playback as usual. As opposed to all earlier VS10XX chips, it is not recommended to do a software reset between songs. This way the user may be sure that even files with low samplerates or bitrates are played right to their end. 10.
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VS1053b Datasheet 10.5.1 10 OPERATION Playing a Whole File This is the default playback mode. 1. 2. 3. 4. 5. 6. Send an audio file to VS1053b. Read extra parameter value endFillByte (Chapter 10.11). Send at least 2052 bytes of endFillByte[7:0]. Set SCI_MODE bit SM_CANCEL. Send at least 32 bytes of endFillByte[7:0]. Read SCI_MODE. If SM_CANCEL is still set, go to 5. If SM_CANCEL hasn’t cleared after sending 2048 bytes, do a software reset (this should be extremely rare). 7.
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VS1053b Datasheet 10.5.4 10 OPERATION Fast Forward and Rewind without Audio To do fast forward and rewind you need the capability to do random access to the audio file. Unfortunately fast forward and rewind isn’t available at all times, like when file headers are being read. 1. Send a portion of an audio file to VS1053b. 2. When random access is required, read SCI_STATUS bit SS_DO_NOT_JUMP. If that bit is set, random access cannot be performed, so go back to 1. 3.
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VS1053b Datasheet 10.6 10 OPERATION Feeding PCM Data VS1053b can be used as a PCM decoder by sending a WAV file header. If the length sent in the WAV header is 0xFFFFFFFF, VS1053b will stay in PCM mode indefinitely (or until SM_CANCEL has been set). 8-bit (unsigned) linear and 16-bit (signed, 2’s complement) linear audio is supported in mono or stereo.
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VS1053b Datasheet 10.8 10 OPERATION PCM / ADPCM Recording This chapter explains how to record a RIFF/WAV file in PCM or IMA ADPCM format. IME ADPCM is a widely supported ADPCM format and many PC audio playback programs can play it. IMA ADPCM recording gives a compression ratio of almost 4:1 compared to linear, 16-bit audio. This makes it possible to record for example ono 8 kHz audio at 32.44 kbit/s.
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VS1053b Datasheet 10 OPERATION WriteVS10xxRegister(SCI_MODE, ReadVS10xxRegister(SCI_MODE) | SM_ADPCM | SM_LINE1); #ifdef I_HAVE_THE_VS1053B_PATCHES_PACKAGE /* Strongly recommended to use the VS1053b Patches package. Get it at http://www.vlsi.fi/en/support/software/vs10xxpatches.
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VS1053b Datasheet 10.8.2 10 OPERATION Reading PCM / IMA ADPCM Data After PCM / IMA ADPCM recording has been activated, registers SCI_HDAT0 and SCI_HDAT1 have new functions. The PCM / IMA ADPCM sample buffer is 1024 16-bit words. The fill status of the buffer can be read from SCI_HDAT1. If SCI_HDAT1 is greater than 0, you can read as many 16-bit words from SCI_HDAT0. If the data is not read fast enough, the buffer overflows and returns to empty state.
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VS1053b Datasheet 10 OPERATION If you know beforehand how much you are going to record, you may fill in the complete header before any actual data. However, if you don’t know how much you are going to record, you have to fill in the header size datas F and D after finishing recording. The PCM data is read from SCI_HDAT0 and written into file as follows. The low 8 bits of SCI_HDAT0 should be written as the first byte to a file, then the high 8 bits (little-endian order).
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VS1053b Datasheet 10 OPERATION If you know beforehand how much you are going to record, you may fill in the complete header before any actual data. However, if you don’t know how much you are going to record, you have to fill in the header size datas F , S and D after finishing recording. The 128 words (256 words for stereo) of an ADPCM block are read from SCI_HDAT0 and written into file as follows.
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VS1053b Datasheet 10.8.7 10 OPERATION Record Monitoring Volume In VS1053b writing to the SCI_VOL register during IMA ADPCM encoding does not change the volume. You need to set a suitable volume before activating the IMA ADPCM mode, or you can use the VS1053 hardware volume control register DAC_VOL directly. For example: WriteVS10xxRegister(SCI_WRAMADDR, 0xc045); WriteVS10xxRegister(SCI_WRAM, 0x0101); /*DAC_VOL*/ /*-6.0 dB*/ The hardware volume control DAC_VOL (address 0xc045) allows 0.
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VS1053b Datasheet 10.9 10 OPERATION SPI Boot If GPIO0 is set with a pull-up resistor to 1 at boot time, VS1053b tries to boot from external SPI memory. SPI boot redefines the following pins: Normal Mode GPIO0 GPIO1 DREQ GPIO2 SPI Boot Mode xCS CLK MOSI MISO The memory has to be an SPI Bus Serial EEPROM with 16-bit or 24-bit addresses. The serial speed used by VS1053b is 245 kHz with the nominal 12.288 MHz clock. The first three bytes in the memory have to be 0x50, 0x26, 0x48. 10.
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VS1053b Datasheet 10.11 10 OPERATION Extra Parameters The following structure is in X memory at address 0x1e02 (note the different location than in VS1033) and can be used to change some extra parameters or get useful information.
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VS1053b Datasheet 10 OPERATION You can see that in the invalid read the low part wraps from 0x0000 to 0xffff while the high part stays the same. In this case the second read gives a valid answer, otherwise always use the value of the first read. The second read is needed when it is possible that the low part wraps around, changing the high part, i.e. when the low part is small. bytesLeft is only decreased by one at a time, so a reread is needed only if the low part is 0. 10.11.
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VS1053b Datasheet 10 OPERATION implement perfect fast forward and rewind for WMA and AAC (ADIF, .mp4 / .m4a). positionMsec is a field that gives the current play position in a file in milliseconds, regardless of rewind and fast forward operations. The value is only available in codecs that can determine the play position from the stream itself. Currently WMA and Ogg Vorbis provide this information. If the position is unknown, this field contains -1.
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VS1053b Datasheet 10.11.3 10 OPERATION AAC Parameter config1 sceFoundMask cpeFoundMask lfeFoundMask playSelect dynCompress dynBoost sbrAndPsStatus Address 0x1e03(7:4) 0x1e2a 0x1e2b 0x1e2c 0x1e2d 0x1e2e 0x1e2f 0x1e30 Usage SBR and PS select Single channel elements found Channel pair elements found Low frequency elements found Play element selection Compress coefficient for DRC, -8192=1.0 Boost coefficient for DRC, 8192=1.
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VS1053b Datasheet config1(7:6) ’00’ ’01’ ’10’ ’11’ 10 OPERATION Usage normal mode, process PS if it is available process PS if it is available, but in downsampled mode reserved disable PS processing AAC decoder can also increase the internal clock automatically when it detects that a file can not be decoded correctly with the current clock. The maximum allowed clock is configured with the SCI_CLOCKF register.
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VS1053b Datasheet 10.11.5 10 OPERATION Ogg Vorbis Parameter gain Address 0x1e2a Usage Preferred Replay Gain offset Ogg Vorbis decoding supports Replay Gain technology. The Replay Gain technology is used to automatically give all songs a matching volume so that the user does not need to adjust the volume setting between songs. If the Ogg Vorbis decoder finds a REPLAYGAIN_ALBUM_GAIN tag in the song header, the tag is parsed and the decoded gain setting is written to the gain parameter.
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VS1053b Datasheet 10.12 10 OPERATION SDI Tests There are several test modes in VS1053b, which allow the user to perform memory tests, SCI bus tests, and several different sine wave tests. All tests, except for the New Sine and Sweep Tests, are started in a similar way: do a hardware reset to VS1053b, then set register SM_MODE bit SM_TESTS, and then send a test command sequence to the SDI bus. Each test is started by sending a 4-byte special command sequence, followed by 4 zeros.
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VS1053b Datasheet 10.12.2 10 OPERATION New Sine and Sweep Tests A more frequency-accurate sine test can be started and controlled from SCI. SCI_AICTRL0 and SCI_AICTRL1 set the sine frequencies for left and right channel, respectively. These registers, volume (SCI_VOL), and samplerate (SCI_AUDATA) can be set before or during the test. Write 0x4020 to SCI_AIADDR to start the test.
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VS1053b Datasheet 10.12.5 10 OPERATION Memory Test Memory test mode is initialized with the 8-byte sequence 0x4D 0xEA 0x6D 0x54 0 0 0 0. After this sequence, wait for 1100000 clock cycles.
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VS1053b Datasheet 11 11 11.1 VS1053B REGISTERS VS1053b Registers Who Needs to Read This Chapter User software is required when a user wishes to add some own functionality like DSP effects to VS1053b. However, most users of VS1053b don’t need to worry about writing their own code, or about this chapter, including those who only download software plug-ins from VLSI Solution’s Web site. Note: Also see VS1063 Hardware Guide for more information, because the hardware is compatible with VS1053. 11.
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VS1053b Datasheet 11 11.3 VS1053B REGISTERS VS1053b Hardware DAC Audio Paths Registers DAC_FCTLL DAC_FCTLH Register DAC_VOL Left Registers DAC_LEFT DAC_RIGHT Sigma−delta modulator DAC SRC Analog driver Right CBUF I2S Resampler SRC Register SRC_CONTROL Registers SRC_LEFT SRC_RIGHT Sidestream SDM Registers SDM_LEFT SDM_RIGHT Register SDM_CONTROL Figure 18: VS1053b ADC and DAC data paths with some data registers Figure 18 presents the VS1053b Hardware DAC audio paths.
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VS1053b Datasheet 11 11.4 VS1053B REGISTERS VS1053b Hardware ADC Audio Paths MICN MICP Microphone amplifier LINE1 Multiplexer ADC LINE2 ADC decimator Registers ADC_DATA_LEFT ADC_DATA_RIGHT Figure 19: VS1053b ADC and DAC data paths with some data registers Figure 18 presents the VS1053b Hardware ADC audio paths. Analog audio may be fed upto two channels: one as a differential signal to MICN/MICP or as a one-sided signal to Line1, and the other as a one-sided signal to Line2.
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VS1053b Datasheet 11 11.5 VS1053b Memory Map X-memory Address Description 0x0000..0x17ff System RAM 0x1800..0x187f User RAM 0x1880..0x197f Stack 0x1980..0x3fff System RAM 0x4000..0xbfff ROM 32k 0xc000..0xc0ff Peripherals 0xc100..0xffff ROM 15.75k 11.6 VS1053B REGISTERS Y-memory Address Description 0x0000..0x17ff System RAM 0x1800..0x187f User RAM 0x1880..0x197f Stack 0x1980..0x3fff System RAM 0x4000..0xdfff ROM 40k 0xe000..0xffff System RAM I-memory Address Description 0x0000..
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VS1053b Datasheet 11 11.
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VS1053b Datasheet 11 VS1053B REGISTERS • Select PLL clock multiplier At the core of the PLL controller is the VCO, a high frequency oscillator, whose oscillation frequency is adjusted to be an integer multiple of some input frequency. As the name “PhaseLocked Loop” suggests, this is done by comparing the phase of the input frequency against the phase of a signal which is derived from the VCO output through frequency division. If the system is stable, e.g.
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VS1053b Datasheet 11 11.10 VS1053B REGISTERS GPIO Reg 0xC017 0xC018 0xC019 Type rw r rw Reset 0 0 0 GPIO registers, prefix GPIO_ Abbrev[bits] Description DDR[9:0] Direction IDATA[11:0] Values read from the pins ODATA[8:0] Values set to the pins GPIO_DIR is used to set the direction of the GPIO pins. 1 means output. GPIO_ODATA remembers its values even if a GPIO_DIR bit is set to input. GPIO_IDATA is used to read the pin states.
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VS1053b Datasheet 11 11.11 VS1053B REGISTERS Interrupt Control Reg 0xC01A 0xC01B 0xC01C 0xC01D Type rw w w rw Reset 0 0 0 0 Interrupt registers, prefix INT_ Abbrev[bits] Description ENABLE[9:0] Interrupt enable GLOB_DIS[-] Write to add to interrupt counter GLOB_ENA[-] Write to subtract from interrupt counter COUNTER[4:0] Interrupt counter INT_ENABLE controls the interrupts.
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VS1053b Datasheet 11 11.12 VS1053B REGISTERS UART RS232 UART implements a serial interface using rs232 standard. Start bit D0 D1 D2 D3 D4 D5 D6 Stop D7 bit Figure 20: RS232 serial interface protocol When the line is idling, it stays in logic high state. When a byte is transmitted, the transmission begins with a start bit (logic zero) and continues with data bits (LSB first) and ends up with a stop bit (logic high). 10 bits are sent for each 8-bit byte frame. 11.12.
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VS1053b Datasheet 11 VS1053B REGISTERS UART_ST_TXRUNNING is set if the transmitter shift register is in operation. 11.12.3 Data UART_DATA A read from UART_DATA returns the received byte in bits 7:0, bits 15:8 are returned as ’0’. If there is no more data to be read, the receiver data register full indicator will be cleared. A receive interrupt will be generated when a byte is moved from the receiver shift register to the receiver data register. A write to UART_DATA sets a byte for transmission.
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VS1053b Datasheet 11 VS1053B REGISTERS Example UART Speeds, fm = 49.152 M Hz Comm. Speed [bps] UART_DIV_D1 UART_DIV_D2 4800 255 40 9600 255 20 14400 233 15 19200 255 10 28800 243 7 38400 159 8 57600 121 7 115200 60 7 11.12.6 UART Interrupts and Operation Transmitter operates as follows: After an 8-bit word is written to the transmit data register it will be transmitted instantly if the transmitter is not busy transmitting the previous byte. When the transmission begins a TX_INTR interrupt will be sent.
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VS1053b Datasheet 11 11.13 VS1053B REGISTERS Timers There are two 32-bit timers that can be initialized and enabled independently of each other. If enabled, a timer initializes to its start value, written by a processor, and starts decrementing every clock cycle. When the value goes past zero, an interrupt is sent, and the timer initializes to the value in its start value register, and continues downcounting. A timer stays in that loop as long as it is enabled.
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VS1053b Datasheet 11 11.13.3 Configuration TIMER_ENABLE Name TIMER_EN_T1 TIMER_EN_T0 11.13.4 VS1053B REGISTERS TIMER_ENABLE Bits Bits Description 1 Enable timer 1 0 Enable timer 0 Timer X Startvalue TIMER_Tx[L/H] The 32-bit start value TIMER_Tx[L/H] sets the initial counter value when the timer is reset. The fi timer interrupt frequency ft = c+1 where fi is the master clock obtained with the clock divider (see Chapter 11.13.2 and c is TIMER_Tx[L/H].
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VS1053b Datasheet 11 11.14 VS1053B REGISTERS I2S DAC Interface The 16-bit I2S Interface makes it possible to attach an external DAC to the system. Note: The samplerate of the audio file and the I2S rate are independent. All audio will be automatically converted to 6.144 MHz for VS1053 DAC and to the configured I2S rate using a high-quality sample-rate converter. Note: In VS1053b the I2S pins share different GPIO pins than in VS1033 to be able to use SPI boot and I2S in the same application.
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VS1053b Datasheet 11 11.15 VS1053B REGISTERS Analog-to-Digital Converter (ADC) ADC modulator registers control Analog-to-Digital conversions of VS1053b. Reg 0xC042 0xC043 0xC044 Type rw r r Reset 0 0 0 ADC Decimator registers, prefix ADC_ Abbrev[bits] Description CONTROL[4:0] ADC control DATA_LEFT ADC left channel data DATA_RIGHT ADC right channel data ADC_CONTROL controls the ADC and its associated decimator unit.
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VS1053b Datasheet 11 11.16 VS1053B REGISTERS Resampler SampleRate Converter (SRC) The resampler SRC makes it possible to catch audio from the DAC path. Note: hardware makes no attempts at low-pass filtering data. If the SRC samplerate is lower than the DAC samplerate, aliasing may and will occur.
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VS1053b Datasheet 11 11.17 VS1053B REGISTERS Sidestream Sigma-Delta Modulator (SDM) The Sidestream Sigma-Delta Modulator makes it possible to insert a digital side stream on top of existing audio. Note: The SDM provides a direct, low-delay side channel to the Sigma-Delta DACs of VS10xx. It makes no attempts at low-pass filtering data. Thus there will be practically no image rejection. If using low samplerates, this may cause audible aliasing distortion.
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VS1053b Datasheet 12 12 VERSION CHANGES Version Changes This chapter describes the lastest and most important changes done to VS1053b 12.1 Changes Between VS1033c and VS1053a/b Firmware, 2007-03-08 Completely new or major changes: • I2S pins are now in GPIO4-GPIO7 and do not overlap with SPI boot pins. • No software reset required between files when used correctly. • Ogg Vorbis decoding added. Non-fatal ogg or vorbis decode errors cause automatic resync. This allows easy rewind and fast forward.
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VS1053b Datasheet 12 VERSION CHANGES • Read and write to YRAM at 0xe000..0xffff added to SCI_WRAMADDR/SCI_WRAM. • The resync parameter (parametric_x.resync) is set to 32767 after reset to allow inifinite resynchronization attempts (or until SM_CANCEL is set). Old operation can be restored by writing 0 to resync after reset. • WMA,AAC: more robust resync. • WMA,AAC: If resync is performed, broadcast mode is automatically activated.
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VS1053b Datasheet 13 13 LATEST DOCUMENT VERSION CHANGES Latest Document Version Changes This chapter describes the latest and most important changes to this document. Version 1.22, 2014-12-19 • Added mention of RIFF 8-bit and 16-bit data signedness to Chapter 10.6, Feeding PCM Data. • Updated telephone number in Chapter 14, Contact Information. Version 1.21, 2014-08-13 • Clarified how Ogg Vorbis set Replay Gain parameters in Chapter 10.11.5, Ogg Vorbis.
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VS1053b Datasheet 14 14 CONTACT INFORMATION Contact Information VLSI Solution Oy Entrance G, 2nd floor Hermiankatu 8 FI-33720 Tampere FINLAND URL: http://www.vlsi.fi/ Phone: +358-50-462-3200 Commercial e-mail: sales@vlsi.fi For technical support or suggestions regarding this document, please participate at http://www.vsdsp-forum.com/ For confidential technical discussions, contact support@vlsi.fi Version: 1.