Datasheet

86
7766F–AVR–11/10
ATmega16/32U4
Note: 1. n = 3, 2, 1or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
11.0.2 External Interrupt Control Register B – EICRB
• Bit 7..6 – Res: Reserved Bits
These bits are reserved bits in the ATmega16U4/ATmega32U4 and always read as zero.
• Bits 5, 4 – ISC61, ISC60: External Interrupt 6 Sense Control Bits
The External Interrupt 6 is activated by the external pin INT6 if the SREG I-flag and the corre-
sponding interrupt mask in the EIMSK is set. The level and edges on the external pin that
activate the interrupt are defined in Table 11-3. The value on the INT6 pin are sampled before
detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock
period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is
enabled. If low level interrupt is selected, the low level must be held until the completion of the
currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will
generate an interrupt request as long as the pin is held low.
Note: 1. When changing the ISC61/ISC60 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
Table 11-1. Interrupt Sense Control
(1)
ISCn1 ISCn0 Description
0 0 The low level of INTn generates an interrupt request.
0 1 Any edge of INTn generates asynchronously an interrupt request.
1 0 The falling edge of INTn generates asynchronously an interrupt request.
1 1 The rising edge of INTn generates asynchronously an interrupt request.
Table 11-2. Asynchronous External Interrupt Characteristics
Symbol Parameter Condition Min Typ Max Units
t
INT
Minimum pulse width for
asynchronous external interrupt
50 ns
Bit 76543210
- - ISC61 ISC60 - - - - EICRB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Table 11-3. Interrupt Sense Control
(1)
ISC61 ISC60 Description
0 0 The low level of INT6 generates an interrupt request.
0 1 Any logical change on INT6 generates an interrupt request
10
The falling edge between two samples of INT6 generates an interrupt
request.
11
The rising edge between two samples of INT6 generates an interrupt
request.