Datasheet

74
7766F–AVR–11/10
ATmega16/32U4
• SCK/PCINT1 – Port B, Bit 1
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a
slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI0 is
enabled as a master, the data direction of this pin is controlled by DDB1. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTB1 bit.
PCINT1, Pin Change Interrupt source 1: The PB7 pin can serve as an external interrupt source.
•SS
/PCINT0 – Port B, Bit 0
SS
: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an
input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven
low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB0.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.
Table 10-4 and Table 10-5 relate the alternate functions of Port B to the overriding signals
shown in Figure 10-5 on page 70. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
PCINT0, Pin Change Interrupt source 0: The PB7 pin can serve as an external interrupt source..
Table 10-4. Overriding Signals for Alternate Functions in PB7.PB4
Signal
Name
PB7/PCINT7/OC0A/
OC1C/RTS
PB6/PCINT6/OC1
B/OC.4B/ADC13
PB5/PCINT5/OC1
A/OC.4B
/ADC12
PB4/PCINT4/A
DC11
PUOE 0 0 0 0
PUOV 0 0 0 0
DDOE 0 0 0 0
DDOV 0 0 0 0
PVOE
OC0/OC1C
ENABLE
OC1B ENABLE OC1A ENABLE 0
PVOV OC0/OC1C OC1B OC1A 0
DIEOE PCINT7 • PCIE0 PCINT6 • PCIE0 PCINT5 • PCIE0 PCINT4 • PCIE0
DIEOV 1 1 1 1
DI PCINT7 INPUT PCINT6 INPUT PCINT5 INPUT PCINT4 INPUT
AIO – – – –