Datasheet

53
7766F–AVR–11/10
ATmega16/32U4
8.0.6 Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period t
TOUT
. Refer to
page 55 for details on operation of the Watchdog Timer.
Figure 8-6. Watchdog Reset During Operation
8.0.7 USB Reset
When the USB controller is enabled and configured with the USB Reset CPU feature enabled
and if a valid USB Reset signalling is detected on the bus, the CPU core is reset but the USB
controller remains enabled and attached. This feature may be used to enhance device reliability.
Figure 8-7. USB Reset During Operation
8.0.8 MCU Status Register – MCUSR
The MCU Status Register provides information on which reset source caused an MCU reset.
• Bit 7..6 - Reserved
These bits are reserved and should be read as 0. Do not set these bits.
CK
CC
CC
USB Traffic
USB Traffic
DP
DM
(USB Lines)
t
USBRSTMIN
End of Reset
Bit 76543210
– – USBRF JTRF WDRF BORF EXTRF PORF MCUSR
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 See Bit Description