Datasheet

51
7766F–AVR–11/10
ATmega16/32U4
device is kept in RESET after V
CC
rise. The RESET signal is activated again, without any delay,
when V
CC
decreases below the detection level.
Figure 8-2. MCU Start-up, RESET
Tied to V
CC
Figure 8-3. MCU Start-up, RESET Extended Externally
8.0.4 External Reset
An External Reset is generated by a low level on the RESET
pin. Reset pulses longer than the
minimum pulse width (see Table 8-1) will generate a reset, even if the clock is not running.
Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the
Reset Threshold Voltage – V
RST
– on its positive edge, the delay counter starts the MCU after
the Time-out period – t
TOUT
– has expired.
Figure 8-4. External Reset During Operation
V
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
CC
V
POR
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
V
CC
V
POR
CC