Datasheet

50
7766F–AVR–11/10
ATmega16/32U4
Figure 8-1. Reset Logic
Notes: 1. The Power-on Reset will not work unless the supply voltage has been below V
POT
(falling)
8.0.3 Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in Table 8-1. The POR is activated whenever V
CC
is below the detection level. The
POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply
voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
Table 8-1. Reset Characteristics
Symbol Parameter Condition Min Typ Max Units
V
POT
Power-on Reset Threshold Voltage (rising) 1.4 2.3 V
Power-on Reset Threshold Voltage (falling)
(1)
1.3 2.3 V
V
POR
V
CC
Start Voltage to ensure internal Power-on
Reset signal
-0.1 +0.1 V
V
CCRR
VCC Rise Rate to ensure internal Power_on
Reset signal
0.3 V/ms
V
RST
RESET Pin Threshold Voltage
0.2
Vcc
0.85
Vcc
V
t
RST
Minimum pulse width on RESET Pin 5V, 25°C 400 ns
MCU Status
Register (MCUSR)
Brown-out
Reset Circuit
BODLEVEL [2..0]
Delay Counters
CKSEL[3:0]
CK
TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA BUS
Clock
Generator
SPIKE
FILTER
Pull-up Resistor
JTRF
JTAG Reset
Register
Watchdog
Oscillator
SUT[1:0]
Power-on Reset
Circuit
USB Reset
Detection
USBRF