Datasheet

7766F–AVR–11/10

ATmega16/32U4

The optimal PLL configuration at 5V is: PLL output frequency = 96 MHz, divided by 1.5 to gener-

ate the 64 MHz High Speed Timer clock, and divided by 2 to generate the 48 MHz USB clock.

0101 56 MHz

0 1 1 0 Not allowed

0111 72 MHz

1000 80 MHz

1001 88 MHz

1010 96 MHz

1 0 1 1 Not allowed

1 1 0 0 Not allowed

1 1 0 1 Not allowed

1 1 1 0 Not allowed

1 1 1 1 Not allowed

PDIV3 PDIV2 PDIV1 PDIV0 PLL Output Frequency