Datasheet

40
7766F–AVR–11/10
ATmega16/32U4
Figure 6-6. PLL Clocking System
6.10.2 PLL Control and Status Register – PLLCSR
• Bit 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega16U4/ATmega32U4 and always read as zero.
• Bit 4 – PINDIV PLL Input Prescaler (1:1, 1:2)
These bits allow to configure the PLL input prescaler to generate the 8MHz input clock for the
PLL from either a 8 or 16 MHz input.
When using a 8 MHz clock source, this bit must be set to 0 before enabling PLL (1:1).
When using a 16 MHz clock source, this bit must be set to 1 before enabling PLL (1:2).
• Bit 3..2 – Res: Reserved Bits
These bits are reserved bits in the ATmega16U4/ATmega32U4 and always read as zero.
• Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started. Note that the Calibrated 8 MHz Internal RC oscillator is
automatically enabled when the PLLE bit is set and with PINMUX (see PLLFRQ register) is set.
The PLL must be disabled before entering Power down mode in order to stop Internal RC Oscil-
lator and avoid extra-consumption.
• Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock. After the PLL is enabled, it
takes about several ms for the PLL to lock. To clear PLOCK, clear PLLE.
6.10.3 PLL Frequency Control Register – PLLFRQ
8 MHz
RC OSCILLATOR
XTAL1
XTAL2
XTAL
OSCILLATOR
PLL
PLLE
Lock
Detector
clk
TMR
To System
Clock Prescaler
clk
8MHz
PLL clock
Prescaler
PINDIV
PDIV3..0
clk
USB
/2
/1.5
PLLTM1:0
PLLUSB
0
1
PINMUX
0
1
01
10
11
CKSEL3:0
PLOCK
Bit 76543210
$29 ($29) PINDIV PLLE PLOCK PLLCSR
Read/Write R R R R/W R R R/W R
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
$32 PINMUX PLLUSB PLLTM1 PLLTM0 PDIV3 PDIV2 PDIV1 PDIV0 PLLFRQ
Read/WriteR/WR/WR/WR/WR/WR/WR/WR/W
Initial Value 0 0 0 0 0 1 0 0