Datasheet

384
7766F–AVR–11/10
ATmega16/32U4
Figure 29-5. SPI Interface Timing Requirements (Slave Mode)
29.8 Hardware Boot EntranceTiming Characteristics
Figure 29-6. Hardware Boot Timing Requirements
MISO
(Data Output)
SCK
(CPOL = 1)
MOSI
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
10
11 11
1213 14
17
15
9
X
16
Table 29-4. Hardware Boot Timings
Symbol Parameter
Min Max
tSHRH
HWB low Setup before Reset High 0
tHHRH
HWB low Hold after Reset High
StartUpTime(
SUT) + Time
Out
Delay(TOUT)
RESET
ALE/HWB
t
SHRH
t
HHRH
Table 29-5. ADC Characteristics
Symbol Parameter Condition Min Typ Max Units
Resolution
Single Ended Conversion 10
BitsDifferential conversion, gain = 1x/10x/40x 8
Differential conversion, gain = 200x 8
TUE Absolute accuracy
V
REF
= 4V, V
CC
= 4V, ADC clock = 200 kHz 2.0 3.0
LSB
Gain = 1x/10x/40x, V
REF
= 4V, V
CC
= 5V,
ADC clock = 200 kHz
2.0 3.0
Gain = 200x, V
REF
= 4V, V
CC
= 5V,
ADC clock = 200 kHz
2.0 4.0