Datasheet

382
7766F–AVR–11/10
ATmega16/32U4
Notes: 1. In ATmega16U4/ATmega32U4, this parameter is characterized and not 100% tested.
2. Required only for f
SCL
> 100 kHz.
3. C
b
= capacitance of one bus line in pF.
4. f
CK
= CPU clock frequency
5. This requirement applies to all ATmega16U4/ATmega32U4 2-wire Serial Interface operation. Other devices connected to the
2-wire Serial Bus need only obey the general f
SCL
requirement.
6. The actual low period generated by the ATmega16U4/ATmega32U4 2-wire Serial Interface is (1/f
SCL
- 2/f
CK
), thus f
CK
must
be greater than 6 MHz for the low time requirement to be strictly met at f
SCL
= 100 kHz.
7. The actual low period generated by the ATmega16U4/ATmega32U4 2-wire Serial Interface is (1/f
SCL
- 2/f
CK
), thus the low
time requirement will not be strictly met for f
SCL
> 308 kHz when f
CK
= 8 MHz. Still, ATmega16U4/ATmega32U4 devices con-
nected to the bus may communicate at full speed (400 kHz) with other ATmega16U4/ATmega32U4 devices, as well as any
other device with a proper t
LOW
acceptance margin.
Figure 29-3. 2-wire Serial Bus Timing
t
HIGH
High period of the SCL clock
f
SCL
≤ 100 kHz 4.0 – µs
f
SCL
> 100 kHz 0.6 – µs
t
SU;STA
Set-up time for a repeated START condition
f
SCL
≤ 100 kHz 4.7 – µs
f
SCL
> 100 kHz 0.6 – µs
t
HD;DAT
Data hold time
f
SCL
≤ 100 kHz 0 3.45 µs
f
SCL
> 100 kHz 0 0.9 µs
t
SU;DAT
Data setup time
f
SCL
≤ 100 kHz 250 – ns
f
SCL
> 100 kHz 100 – ns
t
SU;STO
Setup time for STOP condition
f
SCL
≤ 100 kHz 4.0 – µs
f
SCL
> 100 kHz 0.6 – µs
t
BUF
Bus free time between a STOP and START
condition
f
SCL
≤ 100 kHz 4.7 – µs
f
SCL
> 100 kHz 1.3 – µs
Table 29-2. 2-wire Serial Bus Requirements (Continued)
Symbol Parameter
Condition Min Max Units
t
SU;STA
t
LOW
t
HIGH
t
LOW
t
of
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
BUF
SCL
SDA
t
r