Datasheet

37
7766F–AVR–11/10
ATmega16/32U4
• Bit 7-4 – RCCKSEL[3:0]: CKSEL for RC oscillator
Clock configuration for the RC Oscillator. After a reset, this part of the register is loaded with the
0010b value that corresponds to the RC oscillator. Modifying this value by firmware before
switching to RC oscillator is prohibited because the RC clock will not start.
• Bit 3-0 – EXCKSEL[3:0]: CKSEL for External Clock / Low Power Crystal Oscillator
Clock configuration for the External Clock / Low Power Crystal Oscillator. After a reset, if the
External Clock / Low Power Crystal Oscillator is selected by fuse bits, this part of the register is
loaded with the fuse configuration. Firmware can modify it to change the start-up time after the
clock switch.
See “Device Clocking Options Select(1)” on page 28 for EXCKSEL[3:0] configuration. Only Low
Power Crystal Oscillator, Calibrated Internal RC Oscillator, and External Clock modes are
allowed.
6.8.5 CLKSTA – Clock Status Register
• Bit 7-2 - Reserved bits
These bits are reserved and will always read as zero.
• Bit 1 – RCON: RC Oscillator On
This bit is set by hardware to one if the RC Oscillator is running.
This bit is set by hardware to zero if the RC Oscillator is stopped.
• Bit 0 – EXTON: External Clock / Low Power Crystal Oscillator On
This bit is set by hardware to one if the External Clock / Low Power Crystal Oscillator is running.
This bit is set by hardware to zero if the External Clock / Low Power Crystal Oscillator is
stopped.
6.9 Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-
cuits on the system. The clock also will be output during reset, and the normal operation of I/O
pin will be overridden when the fuse is programmed. Any clock source, including the internal RC
Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is
used, it is the divided system clock that is output.
6.9.1 System Clock Prescaler
The AVR USB has a system clock prescaler, and the system clock can be divided by setting the
“CLKPR – Clock Prescaler Register” on page 38. This feature can be used to decrease the sys-
tem clock frequency and the power consumption when the requirement for processing power is
low. This can be used with all clock source options, and it will affect the clock frequency of the
CPU and all synchronous peripherals. clk
I/O
, clk
ADC
, clk
CPU
, and clk
FLASH
are divided by a factor
as shown in Table 6-10.
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting.
Bit 7 6543210
- - - - - - RCON EXTON CLKSTA
Read/Write R R R R R R R R
Initial Value 0 0 0 0 0