Datasheet
310
7766F–AVR–11/10
ATmega16/32U4
Note: 1. MUX5 bit make part of ADCSRB register
24.9.2 ADC Control and Status Register A – ADCSRA
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the
ADC off while a conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode,
write this bit to one to start the first conversion. The first conversion after ADSC has been written
after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,
will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-
tion of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete,
it returns to zero. Writing zero to this bit has no effect.
• Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-
version on a positive edge of the selected trigger signal. The trigger source is selected by setting
the ADC Trigger Select bits, ADTS in ADCSRB.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the Data Registers are updated. The
ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.
ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alter-
natively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-
110100
N/A
ADC4 ADC1 40x
110101 ADC5 ADC1 40x
110110 ADC6 ADC1 40x
110111 ADC7 ADC1 40x
111000 ADC4 ADC0
200x
111001 ADC5 ADC0
200x
111010 ADC6 ADC0
200x
111011 ADC7 ADC0
200x
111100 ADC4 ADC1
200x
111101 ADC5 ADC1
200x
111110 ADC6 ADC1
200x
111111 ADC7 ADC1
200x
Table 24-4. Input Channel and Gain Selections (Continued)
MUX5..0
(1)
Single Ended Input Positive Differential Input Negative Differential Input Gain
Bit 76543210
ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0