Datasheet

29
7766F–AVR–11/10
ATmega16/32U4
6.2.1 Default Clock Source ATmega16U4 and ATmega32U4
The device is shipped with Low Power Crystal Oscillator (8.0MHz-16MHz) enabled and with the
fuse CKDIV8 programmed, resulting in 1.0MHz system clock with an 8 MHz crystal. See Table
28-5 on page 348 for an overview of the default Clock Selection Fuse setting.
6.2.2 Default Clock Source ATmega16U4RC and ATmega32U4RC
The device is shipped with Calibrated Internal RC oscillator (8.0MHz) enabled and with the fuse
CKDIV8 programmed, resulting in 1.0MHz system clock. See Table 28-5 on page 348 for an
overview of the default Clock Selection Fuse setting.
6.2.3 Clock Startup Sequence
Any clock source needs a sufficient V
CC
to start oscillating and a minimum number of oscillating
cycles before it can be considered stable.
To ensure sufficient V
CC
, the device issues an internal reset with a time-out delay (t
TOUT
) after
the device reset is released by all other reset sources. “On-chip Debug System” on page 48
describes the start conditions for the internal reset. The delay (t
TOUT
) is timed from the Watchdog
Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The
selectable delays are shown in Table 6-2. The frequency of the Watchdog Oscillator is voltage
dependent as shown in Table 6-2.
Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc. The
delay will not monitor the actual voltage and it will be required to select a delay longer than the
Vcc rise time. If this is not possible, an internal or external Brown-Out Detection circuit should be
used. A BOD circuit will ensure sufficient Vcc before it releases the reset, and the time-out delay
can be disabled. Disabling the time-out delay without utilizing a Brown-Out Detection circuit is
not recommended.
The oscillator is required to oscillate for a minimum number of cycles before the clock is consid-
ered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal
reset active for a given number of clock cycles. The reset is then released and the device will
start to execute. The recommended oscillator start-up time is dependent on the clock type, and
varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal.
The start-up sequence for the clock includes both the time-out delay and the start-up time when
the device starts up from reset. When starting up from Power-save or Power-down mode, Vcc is
assumed to be at a sufficient level and only the start-up time is included.
6.3 Low Power Crystal Oscillator
Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be
configured for use as an On-chip Oscillator, as shown in Figure 6-2. Either a quartz crystal or a
ceramic resonator may be used.
This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 out-
put. It gives the lowest power consumption, but is not capable of driving other clock inputs.
Table 6-2. Number of Watchdog Oscillator Cycles
Typ Time-out (V
CC
= 5.0V) Typ Time-out (V
CC
= 3.0V) Number of Cycles
0 ms 0 ms 0
4.1 ms 4.3 ms 512
65 ms 69 ms 8K (8,192)