Datasheet

279
7766F–AVR–11/10
ATmega16/32U4
• 4 - WAKEUPI - Wake-up CPU Interrupt Flag
Set by hardware when the USB controller is re-activated by a filtered non-idle signal from the
lines (not by an upstream resume). This triggers an interrupt if WAKEUPE is set.
Shall be cleared by software (USB clock inputs must be enabled before). Setting by software
has no effect.
See Section 22.8, page 269 for more details.
• 3 - EORSTI - End Of Reset Interrupt Flag
Set by hardware when an “End Of Reset” has been detected by the USB controller. This triggers
an USB interrupt if EORSTE is set.
Shall be cleared by software. Setting by software has no effect.
• 2 - SOFI - Start Of Frame Interrupt Flag
Set by hardware when an USB “Start Of Frame” PID (SOF) has been detected (every 1 ms).
This triggers an USB interrupt if SOFE is set.
• 1 - Reserved
The value read from this bits is always 0. Do not set this bit
• 0 - SUSPI - Suspend Interrupt Flag
Set by hardware when an USB “Suspend” ‘idle bus for 3 frame periods: a J state for 3 ms) is
detected. This triggers an USB interrupt if SUSPE is set.
Shall be cleared by software. Setting by software has no effect.
See Section 22.8, page 269 for more details.
The interrupt bits are set even if their corresponding ‘Enable’ bits is not set.
• 7 - Reserved
The value read from this bits is always 0. Do not set this bit.
• 6 - UPRSME - Upstream Resume Interrupt Enable Bit
Set to enable the UPRSMI interrupt.
Clear to disable the UPRSMI interrupt.
• 5 - EORSME - End Of Resume Interrupt Enable Bit
Set to enable the EORSMI interrupt.
Clear to disable the EORSMI interrupt.
• 4 - WAKEUPE - Wake-up CPU Interrupt Enable Bit
Set to enable the WAKEUPI interrupt.
Clear to disable the WAKEUPI interrupt.
Bit 76543210
- UPRSME EORSME WAKEUPE EORSTE SOFE - SUSPE UDIEN
Read/Write
Initial Value 0 0 0 0 0 0 0 0