Datasheet

274
7766F–AVR–11/10
ATmega16/32U4
22.14 IN endpoint management
IN packets are sent by the USB device controller, upon an IN request from the host. All the data
can be written by the CPU, which acknowledge or not the bank when it is full.Overview
The Endpoint must be configured first.
The TXINI bit is set by hardware when the current bank becomes free. This triggers an interrupt
if the TXINE bit is set. The FIFOCON bit is set at the same time. The CPU writes into the FIFO
and clears the FIFOCON bit to allow the USB controller to send the data. If the IN Endpoint is
composed of multiple banks, this also switches to the next data bank. The TXINI and FIFOCON
bits are automatically updated by hardware regarding the status of the next bank.
TXINI shall always be cleared before clearing FIFOCON.
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can
write data to the bank, and cleared by hardware when the bank is full.
22.14.1 Detailed description
The data are written by the CPU, following the next flow:
• When the bank is empty, an endpoint interrupt (EPINTx) is triggered, if enabled (TXINE set)
and TXINI is set. The CPU can also poll TXINI or FIFOCON, depending the software
architecture choice,
• The CPU acknowledges the interrupt by clearing TXINI,
• The CPU can write the data into the current bank (write in UEDATX),
• The CPU can free the bank by clearing FIFOCON when all the data are written, that is:
IN
DATA
(bank 0)
ACK
TXINI
FIFOCON
HW
Example with 1 IN data bank
write data from CPU
BANK 0
Example with 2 IN data banks
SW
SW SW
SW
IN
IN
DATA
(bank 0)
ACK
TXINI
FIFOCON
write data from CPU
BANK 0
SW
SW SW
SW
IN
DATA
(bank 1)
ACK
write data from CPU
BANK 0
write data from CPU
BANK 1
SW
HW
write data from CPU
BANK0
NAK