Datasheet

264
7766F–AVR–11/10
ATmega16/32U4
• 5 – FRZCLK: Freeze USB Clock Bit
Set to disable the clock inputs (the ”Resume Detection” is still active). This reduces the power
consumption. Clear to enable the clock inputs.
• 4 – OTGPADE: VBUS Pad Enable
Set to enable the VBUS pad. Clear to disable the VBUS pad.
Note that this bit can be set/cleared even if USBE=0. That allows the VBUS detection even if the
USB macro is disable.
• 3-1 – Reserved
The value read from these bits is always 0. Do not set these bits.
• 0 – VBUSTE: VBUS Transition Interrupt Enable Bit
Set this bit to enable the VBUS Transition interrupt generation.
Clear this bit to disable the VBUS Transition interrupt generation.
• 7-2 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 1 - ID: ID status
This bit is always read as “1”, it has been conserved for compatibility with AT90USB64/128 (in
which it indicates the value of the OTG ID pin).
• 0 – VBUS: VBus Flag
The value read from this bit indicates the state of the VBUS pin. This bit can be used in device
mode to monitor the USB bus connection state of the application. See Section 21.11, page 262
for more details.
7-1 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 0 – VBUSTI: IVBUS Transition Interrupt Flag
Set by hardware when a transition (high to low, low to high) has been detected on the VBUS
pad.
Shall be cleared by software.
Bit 76543 2 1 0
----- -IDVBUSUSBSTA
Read/WriteRRRRRRRR
Initial Value00000 0 1 0
Bit 76543210
-------VBUSTIUSBINT
Read/WriteRRRRRRR/WR/W
Initial Value00000000