Datasheet

263
7766F–AVR–11/10
ATmega16/32U4
Figure 21-13. Plug-in Detection Input Block Diagram
The control logic of the VBUS pad outputs a signal regarding the VBUS voltage level:
• The “Session_valid” signal is active high when the voltage on the UVBUS pad is higher or
equal to 1.4V. If lower than 1.4V, the signal is not active.
• The VBUS status bit is set when “Session_valid” signal is active (VBUS > 1.4V).
• The VBUSTI flag is set each time the VBUS state changes.
• The USB peripheral cannot attach to the bus while VBUS bit is not set.
21.12 Registers description
21.12.1 USB general registers
• 7-1 – Reserved
These bits are reserved. Do not modify these bits.
• 0 – UVREGE: USB pad regulator Enable
Set to enable the USB pad regulator. Clear to disable the USB pad regulator.
• 7 – USBE: USB macro Enable Bit
Set to enable the USB controller. Clear to disable and reset the USB controller, to disable the
USB transceiver and to disable the USB controller clock inputs.
• 6 – Reserved
The value read from these bits is always 0. Do not set these bits.
VBUSTI
USBINT.0
VBUS
VBUS
USBSTA.0
VSS
VDD
Pad logic
Session_valid
R
PU
R
PU
Bit 76 5 4 321 0
- - - - - - - UVREGE UHWCON
Read/Write R/W R/W R R/W R R R R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 321 0
USBE - FRZCLK OTGPADE - - - VBUSTE USBCON
Read/Write R/W R/W R/W R/W R R R/W R/W
Initial Value 0 0 1 0 0 0 0 0