Datasheet

260
7766F–AVR–11/10
ATmega16/32U4
21.7.3 Freeze clock
The firmware has the ability to reduce the power consumption by setting the FRZCLK bit, which
freeze the clock of USB controller. When FRZCLK is set, it is still possible to access to the fol-
lowing registers:
• USBCON, USBSTA, USBINT
• UDCON (detach, ...)
•UDINT
•UDIEN
Moreover, when FRZCLK is set, only the following interrupts may be triggered:
• WAKEUPI
•VBUSTI
21.8 Speed Control
The speed selection (Full Speed or Low Speed) depends on the D+/D- pull-up. The LSM bit in
UDCON register allows to select an internal pull up on D- (Low Speed mode) or D+ (Full Speed
mode) data lines.
Figure 21-11. Device mode Speed Selection
21.9 Memory management
The controller only supports the following memory allocation management.
The reservation of a Pipe or an Endpoint can only be made in the increasing order (Pipe/End-
point 0 to the last Pipe/Endpoint). The firmware shall thus configure them in the same order.
The reservation of a Pipe or an Endpoint “k
i
” is done when its ALLOC bit is set. Then, the hard-
ware allocates the memory and inserts it between the Pipe/Endpoints “k
i-1
” and “k
i+1
”. The “k
i+1
”
Pipe/Endpoint memory “slides” up and its data is lost. Note that the “k
i+2
” and upper Pipe/End-
point memory does not slide.
Clearing a Pipe enable (PEN) or an Endpoint enable (EPEN) does not clear either its ALLOC bit,
or its configuration (EPSIZE/PSIZE, EPBK/PBK). To free its memory, the firmware should clear
ALLOC. Then, the “k
i+1
” Pipe/Endpoint memory automatically “slides” down. Note that the “k
i+2
”
and upper Pipe/Endpoint memory does not slide.
R
PU
DETACH
UDCON.0
D+
D-
R
PU
LSM
UDCON.2
UCAP
USB
Regulator