Datasheet

209
7766F–AVR–11/10
ATmega16/32U4
18.10.5 USART Control and Status Register n D– UCSRnD
• Bits 7:2 – Reserved bits
These bits are reserved and will be read as ‘0’. Do not set these bits.
• Bits 1 – CTSEN: UART CTS
Signal Enable
Set this bit by firmware to enable the transmission flow control signal (CTS
). Transmission will
be enabled only if CTS
input = 0. Clear this bit to disable the transmission flow control signal.
Transmission will occur without hardware condition. Data Direction Register bit must be correctly
clear to enable the pin as an input.
• Bits 0 – RTSEN: UART RTS
Signal Enable
Set this bit by firmware to enable the reception flow control signal (RTS). In this case the RTS
line will automatically rise when the FIFO is full. Clear this bit to disable the reception flow control
signal. Data Direction Register bit must be correctly set to enable the pin as an output.
18.10.6 USART Baud Rate Registers – UBRRLn and UBRRHn
• Bit 15:12 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit must be
written to zero when UBRRH is written.
• Bit 11:0 – UBRR11:0: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four
most significant bits, and the UBRRL contains the eight least significant bits of the USART baud
rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is
changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler.
18.11 Examples of Baud Rate Setting
For standard crystal and resonator frequencies, the most commonly used baud rates for asyn-
chronous operation can be generated by using the UBRR settings in Table 18-9 to Table 18-12.
UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate,
are bold in the table. Higher error ratings are acceptable, but the Receiver will have less noise
Bit 7 6 5 4 3 2 1 0
– – – – – – CTSEN RTSEN UCSRnD
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 1514131211109 8
– – – – UBRR[11:8] UBRRHn
UBRR[7:0] UBRRLn
76543210
Read/WriteRRRRR/WR/WR/WR/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
00000000