Datasheet
20
7766F–AVR–11/10
ATmega16/32U4
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O registers, and the 1.25/2.5Kbytes of internal
data SRAM in the ATmega16U4/ATmega32U4 are all accessible through all these addressing
modes. The Register File is described in “General Purpose Register File” on page 12.
Figure 5-2. Data Memory Map
5.2.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
CPU
cycles as described in Figure 5-3.
Figure 5-3. On-chip Data SRAM Access Cycles
32
R
eg
i
st
e
r
s
64
I/O
R
eg
i
st
e
r
s
I
n
t
e
r
na
l
S
R
A
M
$0000
-
$001
F
$0020
-
$005
F
$
FFFF
$0060
-
$00
FF
D
a
t
a
M
e
m
o
r
y
160
E
xt
I/O
R
eg
.
ISRAM end : $05FF / $0AFF
ISRAM start : $0100
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction