Datasheet

183
7766F–AVR–11/10
ATmega16/32U4
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to Figure 17-3 and Figure 17-4 for an example. The CPOL functionality is sum-
marized below:
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to Figure 17-3 and Figure 17-4 for an example. The CPOL
functionality is summarized below:
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f
osc
is
shown in the following table:
17.1.4 SPI Status Register – SPSR
Table 17-2. CPOL Functionality
CPOL Leading Edge Trailing Edge
0 Rising Falling
1 Falling Rising
Table 17-3. CPHA Functionality
CPHA Leading Edge Trailing Edge
0 Sample Setup
1 Setup Sample
Table 17-4. Relationship Between SCK and the Oscillator Frequency
SPI2X SPR1 SPR0 SCK Frequency
000
f
osc
/4
001f
osc
/16
010
f
osc
/64
011
f
osc
/128
100
f
osc
/2
101
f
osc
/8
110
f
osc
/32
111
f
osc
/64
Bit 76543210
SPIF WCOL – – – – – SPI2X SPSR
Read/WriteRRRRRRRR/W
Initial Value00000000