Datasheet

177

7766F–AVR–11/10

ATmega16/32U4

17. Serial Peripheral Interface – SPI

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the

ATmega16U4/ATmega32U4 and peripheral devices or between several AVR devices. The

ATmega16U4/ATmega32U4 SPI includes the following features:

•

Full-duplex, Three-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Seven Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

• Double Speed (CK/2) Master SPI Mode

USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 214.

The Power Reduction SPI bit, PRSPI, in “Power Reduction Register 0 - PRR0” on page 46 on

page 50 must be written to zero to enable SPI module.

Figure 17-1. SPI Block Diagram

(1)

Note: 1. Refer to “Pinout ATmega16U4/ATmega32U4” on page 3, and Table 10-3 on page 72 for SPI

pin placement.

The interconnection between Master and Slave CPUs with SPI is shown in Figure 17-2. The sys-

tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the

SPI2X

DIVIDER

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