Datasheet

166
7766F–AVR–11/10
ATmega16/32U4
• Bits 3 .. 0 - CS43, CS42, CS41, CS40: Clock Select Bits 3, 2, 1, and 0
The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter4.
The Stop condition provides a Timer Enable/Disable function.
15.12.3 TCCR4C – Timer/Counter4 Control Register C
• Bits 7,6 - COM4A1S, COM4A0S: Comparator A Output Mode, Bits 1 and 0
These bits are the shadow bits of the COM4A1 and COM4A0 bits that are described in the sec-
tion “TCCR4A – Timer/Counter4 Control Register A” on page 162.
Table 15-14. Division factors of the Dead Time prescaler
DTPS41 DTPS40 Prescaler divides the T/C4 clock by
0 0 1x (no division)
012x
104x
118x
Table 15-15. Timer/Counter4 Prescaler Select
CS43 CS42 CS41 CS40 Asynchronous Clocking Mode Synchronous Clocking Mode
0000T/C4 stopped T/C4 stopped
0001PCK CK
0010PCK/2 CK/2
0011PCK/4 CK/4
0100PCK/8 CK/8
0101PCK/16 CK/16
0110PCK/32 CK/32
0111PCK/64 CK/64
1000PCK/128 CK/128
1001PCK/256 CK/256
1010PCK/512 CK/512
1011PCK/1024 CK/1024
1100PCK/2048 CK/2048
1101PCK/4096 CK/4096
1110PCK/8192 CK/8192
1111PCK/16384 CK/16384
Bit 76543210
COM4A1S COM4A0S COM4B1S COMAB0S COM4D1 COM4D0 FOC4D PWM4D TCCR4C
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 00000000