Datasheet

156
7766F–AVR–11/10
ATmega16/32U4
15.9 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T4
) is therefore shown as a
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set.
Figure 15-16 contains timing data for basic Timer/Counter operation. The figure shows the count
sequence close to the MAX value in all modes other than Phase and Frequency Correct PWM
Mode. Figure 15-17 shows the same timing data, but with the prescaler enabled, in all modes
other than Phase and Frequency Correct PWM Mode. Figure 15-18 shows the setting of
OCF4A, OCF4B and OCF4D in all modes, and Figure 15-19 shows the setting of TOV4 in
Phase and Frequency Correct PWM Mode.
Figure 15-16. Timer/Counter Timing Diagram, no Prescaling
Figure 15-17. Timer/Counter Timing Diagram, with Prescaler (f
clkT4
/8)
10OC4A • OC4OE2 OC4A • OC4OE3
11OC4A • OC4OE2 OC4A • OC4OE3
COM4D1 COM4D0 OC4D Pin (PD6) OC4D Pin (PD7)
0 0 Disconnected Disconnected
01OC4A
• OC4OE4 OC4A • OC4OE5
10OC4A • OC4OE4 OC4A • OC4OE5
11OC4A • OC4OE4 OC4A • OC4OE5
Table 15-5. Output Compare Pin configurations in PWM6 Mode (Continued)
COM4A1 COM4A0 OC4A Pin (PC6) OC4A Pin (PC7)
clk
Tn
(clk
PCK
/1)
TOVn
clk
PCK
TCNTn TOP - 1 TOP BOTTOM BOTTOM + 1
TOVn
TCNTn
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
PCK
clk
Tn
(clk
PCK
/8)