Datasheet

155

7766F–AVR–11/10

ATmega16/32U4

counter value matches the TOP value. The counter is then cleared at the following timer clock

cycle. The TCNT4 value is in the timing diagram shown as a histogram for illustrating the single-

slope operation. The timing diagram includes Output Compare pins OC4A

and OC4A, and the

corresponding Output Compare Override Enable bits (OC4OE1..OC4OE0).

Figure 15-15. PWM6 Mode, Single-slope Operation, Timing Diagram

The general I/O port function is overridden by the Output Compare value (OC4x / OC4x

) from

the Dead Time Generator if either of the COM4x1:0 bits are set. The Output Compare pins can

also be overridden by the Output Compare Override Enable bits OC4OE5..OC4OE0. If an Over-

ride Enable bit is cleared, the actual value from the port register will be visible on the port pin

and, if the Override Enable bit is set, the Output Compare pin is allowed to be connected on the

port pin. The Output Compare Pin configurations are described in Table 15-5.

Table 15-5. Output Compare Pin configurations in PWM6 Mode

COM4A1 COM4A0 OC4A Pin (PC6) OC4A Pin (PC7)

0 0 Disconnected Disconnected

01OC4A

• OC4OE0 OC4A • OC4OE1

10OC4A • OC4OE0 OC4A • OC4OE1

11OC4A • OC4OE0 OC4A • OC4OE1

COM4B1 COM4B0 OC4B Pin (PB5) OC4B Pin (PB6)

0 0 Disconnected Disconnected

01OC4A • OC4OE2 OC4A • OC4OE3

TCNT4

OC4A Pin

OC4B Pin

OC4D Pin

OC4OE0

OC4OE1

OC4OE2

OC4OE3

OC4OE4

OC4OE5

OCW4A