Datasheet

133
7766F–AVR–11/10
ATmega16/32U4
If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
14.10.5 Timer/Counter1 Control Register C – TCCR1C
14.10.6 Timer/Counter3 Control Register C – TCCR3C
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Bit 7 – FOCnA: Force Output Compare for Channel A
The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM
mode. When writing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate compare
match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed
according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are imple-
mented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the
effect of the forced compare.
A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear
Timer on Compare Match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB/FOCnB bits are always read as zero.
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Bit 4:0 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be written to zero when TCCRnC is written.
Table 14-6. Clock Select Bit Description
CSn2 CSn1 CSn0 Description
0 0 0 No clock source. (Timer/Counter stopped)
001clk
I/O
/1 (No prescaling
010clk
I/O
/8 (From prescaler)
011clk
I/O
/64 (From prescaler)
100clk
I/O
/256 (From prescaler)
101clk
I/O
/1024 (From prescaler)
1 1 0 External clock source on Tn pin. Clock on falling edge
1 1 1 External clock source on Tn pin. Clock on rising edge
Bit 7654 3 210
FOC1A FOC1B FOC1C – – – – – TCCR1C
Read/Write W W W R R R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 7654 3 210
FOC3A––– – –––TCCR3C
Read/WriteWRRR R RRR
Initial Value 0 0 0 0 0 0 0 0