Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • – 135 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-Chip 2-cycle Multiplier Non-volatile Program and Data Memories – 16/32K Bytes of In-System Self-Programmable Flash (ATmega16U4/ATmega32U4) – 1.25/2.
ATmega16/32U4 • • • • • – Byte Oriented 2-wire Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change – On-chip Temperature Sensor Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal 8 MHz Calibrated Oscillator – Internal clock prescaler & On-the-fly Clock Switching (Int RC / Ext Osc) – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reductio
ATmega16/32U4 1. Pin Configurations (INT.6/AIN0) PE6 UVcc AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC 43 42 41 40 39 38 37 36 35 34 Pinout ATmega16U4/ATmega32U4 44 Figure 1-1.
ATmega16/32U4 Block Diagram PF7 - PF4 VCC PC7 PC6 PF1 PF0 PORTF DRIVERS RESET Block Diagram XTAL2 Figure 2-1. XTAL1 2.1 PORTC DRIVERS GND DATA REGISTER PORTF DATA DIR. REG. PORTF DATA REGISTER PORTC DATA DIR. REG.
ATmega16/32U4 channels 10-bit ADC with optional differential input stage with programmable gain, an on-chip calibrated temperature sensor, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning.
ATmega16/32U4 Only bits 6 and 7 are present on the product pinout. Port C also serves the functions of special features of the ATmega16U4/ATmega32U4 as listed on page 75. 2.2.5 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability.
ATmega16/32U4 2.2.11 UVCC USB Pads Internal Regulator Input supply voltage. 2.2.12 UCAP USB Pads Internal Regulator Output supply voltage. Should be connected to an external capacitor (1µF). 2.2.13 VBUS USB VBUS monitor input. 2.2.14 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 8-1 on page 50. Shorter pulses are not guaranteed to generate a reset. 2.2.
ATmega16/32U4 3. About 3.1 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 3.2 Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 3.
ATmega16/32U4 4. AVR CPU Core 4.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.2 Architectural Overview Figure 4-1.
ATmega16/32U4 The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
ATmega16/32U4 4.4 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
ATmega16/32U4 • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 4.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATmega16/32U4 Figure 4-3. The X-, Y-, and Z-registers 15 XH XL 7 X-register 0 R27 (0x1B) YH YL 7 0 R29 (0x1D) Z-register 0 R26 (0x1A) 15 Y-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.
ATmega16/32U4 4.6.1 Extended Z-pointer Register for ELPM/SPM - RAMPZ Bit 7 6 5 4 3 2 1 RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 0 RAMPZ0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 RAMPZ For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 4-4. Note that LPM is not affected by the RAMPZ setting. Figure 4-4.
ATmega16/32U4 Figure 4-6. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 4.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space.
ATmega16/32U4 Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction.
ATmega16/32U4 Assembly Code Example sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 4.8.1 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is five clock cycles minimum.
ATmega16/32U4 5. AVR ATmega16U4/ATmega32U4 Memories This section describes the different memories in the ATmega16U4/ATmega32U4. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega16U4/ATmega32U4 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. Table 5-1. Memory Mapping.
ATmega16/32U4 “Memory Programming” on page 346 contains a detailed description on Flash data serial downloading using the SPI pins or the JTAG interface. Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program Memory instruction description and ELPM - Extended Load Program Memory instruction description). Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 14. Figure 5-1.
ATmega16/32U4 The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O registers, and the 1.25/2.5Kbytes of internal data SRAM in the ATmega16U4/ATmega32U4 are all accessible through all these addressing modes.
ATmega16/32U4 5.3 EEPROM Data Memory The ATmega16U4/ATmega32U4 contains 512Bytes/1K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
ATmega16/32U4 • Bits 7..0 – EEDR7.0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 5.3.
ATmega16/32U4 wise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEPE becomes zero. 2. Wait until SELFPRGEN in SPMCSR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR. 6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.
ATmega16/32U4 Assembly Code Example(1) EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write logical one to EEMPE sbi EECR,EEMPE ; Start eeprom write by setting EEPE sbi EECR,EEPE ret C Code Example(1) void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<
ATmega16/32U4 Assembly Code Example(1) EEPROM_read: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_read ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ; Read data from Data Register in r16,EEDR ret C Code Example(1) unsigned char EEPROM_read(unsigned int uiAddress) { /* Wait for completion of previous write */ while(EECR & (1<
ATmega16/32U4 5.4 I/O Memory The I/O space definition of the ATmega16U4/ATmega32U4 is shown in “Register Summary” on page 408. All ATmega16U4/ATmega32U4 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
ATmega16/32U4 6. System Clock and Clock Options 6.1 Clock Systems and their Distribution Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 43. The clock systems are detailed below. Figure 6-1.
ATmega16/32U4 6.1.4 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 6.1.5 PLL Prescaler Clock – clkPllPresc The PLL requires a 8 MHz input. A prescaler allows user to use either a 8MHz or a 16MHz source (from a crystal or an external source), using a divider (by 2) if necessary.
ATmega16/32U4 6.2.1 Default Clock Source ATmega16U4 and ATmega32U4 The device is shipped with Low Power Crystal Oscillator (8.0MHz-16MHz) enabled and with the fuse CKDIV8 programmed, resulting in 1.0MHz system clock with an 8 MHz crystal. See Table 28-5 on page 348 for an overview of the default Clock Selection Fuse setting. 6.2.2 Default Clock Source ATmega16U4RC and ATmega32U4RC The device is shipped with Calibrated Internal RC oscillator (8.
ATmega16/32U4 C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 6-3. For ceramic resonators, the capacitor values given by the manufacturer should be used. Figure 6-2.
ATmega16/32U4 Table 6-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection (Continued) Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT1..0 Ceramic resonator, slowly rising power 1K CK 14CK + 65 ms(2) 1 00 Crystal Oscillator, BOD enabled 16K CK 14CK 1 01 Crystal Oscillator, fast rising power 16K CK 14CK + 4.
ATmega16/32U4 Note: 6.5 1. These options should only be used if frequency stability at start-up is not important for the application. Calibrated Internal RC Oscillator The calibrated internal RC Oscillator by default provides a 8.0 MHz clock. This frequency is nominal value at 3V and 25°C. The device is shipped with the CKDIV8 Fuse programmed. See “System Clock Prescaler” on page 37 for more details. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 6-7.
ATmega16/32U4 The temperature sensitivity is quite linear but as said previously depends on the process. To determine its slope, the frequency must be measured at two temperatures. The temperature sensor of the ATmega16U4/ATmega32U4 allows such an operation, that is detailed on Section 24.6.1 ”Sensor Calibration” on page 300. It is then possible to calibrate the oscillator frequency in function of the temperature measured.
ATmega16/32U4 Table 6-9. Start-up Times for the External Clock Selection Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) SUT1..0 BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4.1 ms 01 Slowly rising power 6 CK 14CK + 65 ms 10 Power Conditions Reserved 11 When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU.
ATmega16/32U4 Figure 6-4. Example of clock switching with wake-up from USB Host resume 1 Resume from Host USB non-Idle Idle CPU Clock non-Idle (Suspend) Ext 1 RC Ext External Oscillator RC oscillator 3ms Figure 6-5. w atchdog wake-up from power-down Example of clock switching with wake-up from Device upstream-resume 2 Upstream Resume from device USB non-Idle Idle CPU Clock non-Idle (Suspend) Ext RC 2 Ext External Oscillator RC oscillator 3ms 6.8 6.8.
ATmega16/32U4 6.8.2 Switch from RC clock to external clock if (Usb_wake_up_detected()) // if (UDINT.WAKEUPI == 1) { Usb_ack_wake_up(); // UDINT.WAKEUPI = 0; Enable_external_clock(); // CKSEL0.EXTE = 1; while (!External_clock_ready()); // while (CLKSTA.EXTON != 1); Select_external_clock(); // CLKSEL0.CLKS = 1; Enable_pll(); // PLLCSR.PLLE = 1; Disable_RC_clock(); // CLKSEL0.RCE = 0; while (!Pll_ready()); // while (PLLCSR.PLOCK != 1); Usb_unfreeze_clock(); // USBCON.FRZCLK = 0; } 6.8.
ATmega16/32U4 • Bit 7-4 – RCCKSEL[3:0]: CKSEL for RC oscillator Clock configuration for the RC Oscillator. After a reset, this part of the register is loaded with the 0010b value that corresponds to the RC oscillator. Modifying this value by firmware before switching to RC oscillator is prohibited because the RC clock will not start. • Bit 3-0 – EXCKSEL[3:0]: CKSEL for External Clock / Low Power Crystal Oscillator Clock configuration for the External Clock / Low Power Crystal Oscillator.
ATmega16/32U4 The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to the other cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active.
ATmega16/32U4 the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 6-10. 6.
ATmega16/32U4 Figure 6-6. PLL Clocking System CKSEL3:0 PINDIV PINMUX PLOCK PLLE PLLTM1:0 /1.5 Lock Detector XTAL1 XTAL2 10 01 XTAL OSCILLATOR clk TMR 11 PLL clock Prescaler 0 RC OSCILLATOR 8 MHz 1 PLL clk 8MHz /2 1 To System Clock Prescaler clk USB 0 PDIV3..0 PLLUSB 6.10.2 PLL Control and Status Register – PLLCSR Bit 7 6 5 $29 ($29) 4 3 2 1 PINDIV 0 PLLE PLOCK Read/Write R R R R/W R R R/W R Initial Value 0 0 0 0 0 0 0 0 PLLCSR • Bit 7..
ATmega16/32U4 • Bit 7– PINMUX: PLL Input Multiplexer This bit selects the clock input of the PLL: – PINMUX = 0: the PLL input is connected to the PLL Prescaler, that has the Primary System Clock as source – PINMUX = 1: the PLL input is directly connected to the Internal Calibrated 8MHz RC Oscillator. This mode allows to work in USB Low Speed mode with no crystal or using a crystal with a value different of 8/16MHz.
ATmega16/32U4 PDIV3 PDIV2 PDIV1 PDIV0 PLL Output Frequency 0 1 0 1 56 MHz 0 1 1 0 Not allowed 0 1 1 1 72 MHz 1 0 0 0 80 MHz 1 0 0 1 88 MHz 1 0 1 0 96 MHz 1 0 1 1 Not allowed 1 1 0 0 Not allowed 1 1 0 1 Not allowed 1 1 1 0 Not allowed 1 1 1 1 Not allowed The optimal PLL configuration at 5V is: PLL output frequency = 96 MHz, divided by 1.5 to generate the 64 MHz High Speed Timer clock, and divided by 2 to generate the 48 MHz USB clock.
ATmega16/32U4 7. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed.
ATmega16/32U4 7.1 Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the USB, SPI, USART, Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.
ATmega16/32U4 7.5 Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles. 7.6 Extended Standby Mode When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Extended Standby mode.
ATmega16/32U4 7.7.1 Power Reduction Register 0 - PRR0 Bit 7 6 5 4 3 2 1 0 PRTWI PRTIM2 PRTIM0 – PRTIM1 PRSPI - PRADC Read/Write R/W R/W R/W R R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 PRR0 • Bit 7 - PRTWI: Power Reduction TWI Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI again, the TWI should be re initialized to ensure proper operation.
ATmega16/32U4 • Bit 4- PRTIM4: Power Reduction Timer/Counter4 Writing a logic one to this bit shuts down the Timer/Counter4 module. When the Timer/Counter4 is enabled, operation will continue like before the shutdown. • Bit 3 - PRTIM3: Power Reduction Timer/Counter3 Writing a logic one to this bit shuts down the Timer/Counter3 module. When the Timer/Counter3 is enabled, operation will continue like before the shutdown. • Bit 2..1 - Res: Reserved bits These bits are reserved and will always read as zero.
ATmega16/32U4 turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Voltage Reference” on page 54 for details on the start-up time. 7.8.5 Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power.
ATmega16/32U4 8. System Control and Reset 8.0.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
ATmega16/32U4 Figure 8-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF JTRF USBRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor SPIKE FILTER JTAG Reset Register USB Reset Detection Watchdog Oscillator Clock Generator Delay Counters CK TIMEOUT CKSEL[3:0] SUT[1:0] Table 8-1.
ATmega16/32U4 device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay, when VCC decreases below the detection level. Figure 8-2. MCU Start-up, RESET Tied to VCC VCC VPOR VPOT VRST RESET tTOUT TIME-OUT INTERNAL RESET Figure 8-3. MCU Start-up, RESET Extended Externally VCC RESET VPOR VPOT VRST tTOUT TIME-OUT INTERNAL RESET 8.0.4 External Reset An External Reset is generated by a low level on the RESET pin.
ATmega16/32U4 8.0.5 Brown-out Detection ATmega16U4/ATmega32U4 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2. Table 8-2. BODLEVEL Fuse Coding BODLEVEL 2..
ATmega16/32U4 8.0.6 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 55 for details on operation of the Watchdog Timer. Figure 8-6. Watchdog Reset During Operation CC CK 8.0.
ATmega16/32U4 • Bit 5– USBRF: USB Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
ATmega16/32U4 ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. Table 8-4. Symbol Parameter Condition Min Typ Max Units TBD 1.1 TBD V VBG Bandgap reference voltage TBD tBG Bandgap reference start-up time TBD 40 70 µs IBG Bandgap reference current consumption TBD 10 TBD µA Note: 8.2 Internal Voltage Reference Characteristics(1) 1.
ATmega16/32U4 expires. This is typically used to prevent system hang-up in case of runaway code. The third mode, Interrupt and System Reset mode, combines the other two modes by first giving an interrupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown by saving critical parameters before a system reset. The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode.
ATmega16/32U4 Assembly Code Example(1) WDT_off: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in r16, MCUSR andi r16, (0xff & (0<
ATmega16/32U4 The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Assembly Code Example(1) WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence in r16, WDTCSR ori r16, (1<
ATmega16/32U4 handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed. • Bit 6 - WDIE: Watchdog Interrupt Enable When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled.
ATmega16/32U4 . Table 8-6. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V 0 0 0 0 2K (2048) cycles 16 ms 0 0 0 1 4K (4096) cycles 32 ms 0 0 1 0 8K (8192) cycles 64 ms 0 0 1 1 16K (16384) cycles 0.125 s 0 1 0 0 32K (32768) cycles 0.25 s 0 1 0 1 64K (65536) cycles 0.5 s 0 1 1 0 128K (131072) cycles 1.0 s 0 1 1 1 256K (262144) cycles 2.0 s 1 0 0 0 512K (524288) cycles 4.
ATmega16/32U4 9. Interrupts This section describes the specifics of the interrupt handling as performed in ATmega16U4/ATmega32U4. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 15. 9.1 Interrupt Vectors in ATmega16U4/ATmega32U4 Table 9-1. Reset and Interrupt Vectors Vector No.
ATmega16/32U4 Table 9-1. Reset and Interrupt Vectors (Continued) Vector No.
ATmega16/32U4 9.1.2 MCU Control Register – MCUCR Bit 7 6 5 4 3 2 1 0 JTD – – PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash.
ATmega16/32U4 Assembly Code Example Move_interrupts: ; Enable change of Interrupt Vectors ldi r16, (1<
ATmega16/32U4 10. I/O-Ports 10.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
ATmega16/32U4 Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 10.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 10-2.
ATmega16/32U4 If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 10.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 10.2.
ATmega16/32U4 Figure 10-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
ATmega16/32U4 Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
ATmega16/32U4 10.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
ATmega16/32U4 Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. All other signals are unique for each pin. Table 10-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 10-5 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 10-2.
ATmega16/32U4 10.3.1 MCU Control Register – MCUCR Bit 7 6 5 4 3 2 1 0 JTD – – PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 66 for more details about this feature. 10.3.
ATmega16/32U4 • OC1B/PCINT6/OC.4B/ADC12, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set “one”) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. PCINT6, Pin Change Interrupt source 6: The PB7 pin can serve as an external interrupt source. OC.4B: Timer 4 Output Compare B.
ATmega16/32U4 • SCK/PCINT1 – Port B, Bit 1 SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI0 is enabled as a master, the data direction of this pin is controlled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit. PCINT1, Pin Change Interrupt source 1: The PB7 pin can serve as an external interrupt source.
ATmega16/32U4 Table 10-5. 10.3.3 Overriding Signals for Alternate Functions in PB3.
ATmega16/32U4 • OC.3A/OC.4A – Port C, Bit 6 OC.3A: Timer 3 Output Compare A. This pin can be used to generate a PWM signal from Timer 3 module. OC.4A: Timer 4 Output Compare A. This pin can be used to generate a high-speed PWM signal from Timer 4 module, complementary to OC.4A (PC7) signal. The pin has to be configured as an output (DDC6 set “one”) to serve this function. Table 10-7 relate the alternate functions of Port C to the overriding signals shown in Figure 10-5 on page 70. Table 10-7.
ATmega16/32U4 10.3.4 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 10-8. Table 10-8. Port Pin Port D Pins Alternate Functions Alternate Function PD7 T0/OC.4D/ADC10 (Timer/Counter0 Clock Input or Timer 4 Output Compare D / PWM output or Analog to Digital Converter channel 10) PD6 T1/OC.
ATmega16/32U4 • INT3/TXD1 – Port D, Bit 3 INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt source to the MCU. TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is enabled, this pin is configured as an output regardless of the value of DDD3. • INT2/RXD1 – Port D, Bit 2 INT2, External Interrupt source 2. The PD2 pin can serve as an External Interrupt source to the MCU. RXD1, Receive Data (Data input pin for the USART1).
ATmega16/32U4 Table 10-9. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PD7/T0/ OC4D/ADC10 PD6/T1/ OC4D/ADC9 PD5/XCK1/CTS PD4/ICP1/ ADC8 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 XCK1 OUTPUT ENABLE 0 DDOV 0 0 1 0 PVOE 0 0 XCK1 OUTPUT ENABLE 0 PVOV 0 0 XCK1 OUTPUT 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI T0 INPUT T1 INPUT XCK1 INPUT ICP1 INPUT AIO – – – – Table 10-10. Overriding Signals for Alternate Functions in PD3.
ATmega16/32U4 10.3.5 Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 10-11. Table 10-11. Port E Pins Alternate Functions Port Pin Alternate Function PE7 Not present on pin-out. PE6 INT6/AIN0 (External Interrupt 6 Input or Analog Comparator Positive Input) PE5 PE4 Not present on pin-out. PE3 PE2 HWB (Hardware bootloader activation) PE1 Not present on pin-out.
ATmega16/32U4 enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs. Table 10-13. Port F Pins Alternate Functions Port Pin Alternate Function PF7 ADC7/TDI (ADC input channel 7 or JTAG Test Data Input) PF6 ADC6/TDO (ADC input channel 6 or JTAG Test Data Output) PF5 ADC5/TMS (ADC input channel 5 or JTAG Test Mode Select) PF4 ADC4/TCK (ADC input channel 4 or JTAG Test ClocK) PF3 Not present on pin-out.
ATmega16/32U4 . Table 10-14. Overriding Signals for Alternate Functions in PF7..PF4 Signal Name PF7/ADC7/TDI PF6/ADC6/TDO PF5/ADC5/TMS PF4/ADC4/TCK PUOE JTAGEN JTAGEN JTAGEN JTAGEN PUOV 1 0 1 1 DDOE JTAGEN JTAGEN JTAGEN JTAGEN DDOV 0 SHIFT_IR + SHIFT_DR 0 0 PVOE 0 JTAGEN 0 0 PVOV 0 TDO 0 0 DIEOE JTAGEN JTAGEN JTAGEN JTAGEN DIEOV 0 0 0 0 DI – – – – AIO TDI/ADC7 INPUT ADC6 INPUT TMS/ADC5 INPUT TCK/ADC4 INPUT Table 10-15.
ATmega16/32U4 10.4.2 Port B Data Direction Register – DDRB Bit 10.4.
ATmega16/32U4 10.4.10 Port E Data Register – PORTE Bit 10.4.
ATmega16/32U4 11. External Interrupts The External Interrupts are triggered by the INT6, INT3:0 pin or any of the PCINT7..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT[6;3:0] or PCINT7..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The Pin change interrupt PCI0 will trigger if any enabled PCINT7:0 pin toggles. PCMSK0 Register control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT7 ..
ATmega16/32U4 Interrupt Sense Control(1) Table 11-1. ISCn1 ISCn0 0 0 The low level of INTn generates an interrupt request. 0 1 Any edge of INTn generates asynchronously an interrupt request. 1 0 The falling edge of INTn generates asynchronously an interrupt request. 1 1 The rising edge of INTn generates asynchronously an interrupt request. Note: 1. n = 3, 2, 1or 0. When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register.
ATmega16/32U4 • Bit 3..0 – Res: Reserved Bits These bits are reserved bits in the ATmega16U4/ATmega32U4 and always read as zero. 11.0.3 External Interrupt Mask Register – EIMSK Bit 7 6 5 4 3 2 1 0 - INT6 - - INT3 INT2 INT1 IINT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EIMSK • Bits 7..
ATmega16/32U4 • Bit 0 – PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. 11.0.
ATmega16/32U4 12. Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers Timer/Counter0, 1, and 3 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to all Timer/Counters. Tn is used as a general name, n = 0, 1 or 3. 12.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
ATmega16/32U4 Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem).
ATmega16/32U4 13. 8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event management) and wave generation. The main features are: • • • • • • • 13.
ATmega16/32U4 The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B). See “Output Compare Unit” on page 93. for details. The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt request. 13.1.
ATmega16/32U4 clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0).
ATmega16/32U4 Figure 13-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
ATmega16/32U4 generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes.
ATmega16/32U4 13.5.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 13-2 on page 102. For fast PWM mode, refer to Table 13-3 on page 102, and for phase correct PWM refer to Table 13-4 on page 103.
ATmega16/32U4 Figure 13-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega16/32U4 PWM mode is shown in Figure 13-6. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0. Figure 13-6.
ATmega16/32U4 feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 13.6.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM.
ATmega16/32U4 one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 13-4 on page 103). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output.
ATmega16/32U4 Figure 13-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 13-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 13-10.
ATmega16/32U4 13.8 8-bit Timer/Counter Register Description 13.8.1 Timer/Counter Control Register A – TCCR0A Bit 7 6 5 4 3 2 1 0 COM0A 1 COM0A 0 COM0B 1 COM0B 0 – – WGM0 1 WGM0 0 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bits 7:6 – COM01A:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior.
ATmega16/32U4 Table 13-4 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 13-4. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. 1 1 Set OC0A on Compare Match when up-counting.
ATmega16/32U4 Table 13-4 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Compare Output Mode, Phase Correct PWM Mode(1) Table 13-7. COM0A1 COM0A0 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting. 1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting. Note: Description 1.
ATmega16/32U4 13.8.2 Timer/Counter Control Register B – TCCR0B Bit 7 6 5 4 3 2 1 0 FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode.
ATmega16/32U4 Table 13-9. Clock Select Bit Description (Continued) CS02 CS01 CS00 Description 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge. If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting.
ATmega16/32U4 • Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter Interrupt Flag Register – TIFR0.
ATmega16/32U4 14. 16-bit Timers/Counters (Timer/Counter1 and Timer/Counter3) The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • • • • • • • • • • • 14.1 True 16-bit Design (i.e.
ATmega16/32U4 Figure 14-1. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic TCLK Clock Select (2) Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCFnA (Int.Req.) Waveform Generation = OCnA OCRnA OCFnB (Int.Req.) Fixed TOP Values Waveform Generation DATABUS = OCnB OCRnB OCFnC (Int.Req.) Waveform Generation = OCnC OCRnC ( From Analog Comparator Ouput ) ICFn (Int.Req.
ATmega16/32U4 The double buffered Output Compare Registers (OCRnA/B/C) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OCnA/B/C). See “Output Compare Units” on page 117.. The compare match event will also set the Compare Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request.
ATmega16/32U4 Assembly Code Examples(1) ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... C Code Examples(1) unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn; ... Note: 1. See “Code Examples” on page 8. The assembly code example returns the TCNTn value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations.
ATmega16/32U4 Assembly Code Example(1) TIM16_ReadTCNTn: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) unsigned int TIM16_ReadTCNTn( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNTn into i */ i = TCNTn; /* Restore global interrupt flag */ SREG = sreg; return i; } No
ATmega16/32U4 The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
ATmega16/32U4 14.4 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 14-2 shows a block diagram of the counter and its surroundings. Figure 14-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
ATmega16/32U4 The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 14.5 Input Capture Unit The Timer/Counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence.
ATmega16/32U4 Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied into the high byte Temporary Register (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP Register. The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for defining the counter’s TOP value.
ATmega16/32U4 Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be cleared by software (writing a logical one to the I/O bit location).
ATmega16/32U4 The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCRnx Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
ATmega16/32U4 14.7 Compare Match Output Unit The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 14-5 shows a simplified schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
ATmega16/32U4 non-PWM modes refer to Table 14-2 on page 130. For fast PWM mode refer to Table 14-3 on page 130, and for phase correct and phase and frequency correct PWM refer to Table 14-4 on page 131. A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOCnx strobe bits. 14.8 Modes of Operation The mode of operation, i.e.
ATmega16/32U4 Figure 14-6. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega16/32U4 The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX).
ATmega16/32U4 to be written anytime. When the OCRnA I/O location is written the value written will be put into the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNTn matches TOP. The update is done at the same timer clock cycle as the TCNTn is cleared and the TOVn Flag is set. Using the ICRn Register for defining TOP works well when using fixed TOP values.
ATmega16/32U4 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following equation: ( TOP + 1 ) R PCPWM = log ----------------------------------log ( 2 ) In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn (WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11).
ATmega16/32U4 ister. Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output.
ATmega16/32U4 the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: log ( TOP + 1 ) R PFCPWM = ----------------------------------log ( 2 ) In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The counter has then reached the TOP and changes the count direction.
ATmega16/32U4 Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCRnA as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins.
ATmega16/32U4 Figure 14-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 14-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
ATmega16/32U4 Figure 14-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) New OCRnx Value 14.10 16-bit Timer/Counter Register Description 14.10.1 Timer/Counter1 Control Register A – TCCR1A Bit 14.10.
ATmega16/32U4 When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is dependent of the WGMn3:0 bits setting. Table 14-2 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM). Table 14-2. Compare Output Mode, non-PWM COMnA1/COMnB1/ COMnC1 COMnA0/COMnB0/ COMnC0 0 0 Normal port operation, OCnA/OCnB/OCnC disconnected. 0 1 Toggle OCnA/OCnB/OCnC on compare match.
ATmega16/32U4 Table 14-4. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM COMnA1/COMnB/ COMnC1 COMnA0/COMnB0/ COMnC0 0 0 Normal port operation, OCnA/OCnB/OCnC disconnected. 1 WGM13:0 = 8, 9 10 or 11: Toggle OC1A on Compare Match, OC1B and OC1C disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B/OC1C disconnected. 0 Clear OCnA/OCnB/OCnC on compare match when up-counting. Set OCnA/OCnB/OCnC on compare match when downcounting.
ATmega16/32U4 Waveform Generation Mode Bit Description (Continued)(1) Table 14-5. Mode WGMn3 WGMn2 (CTCn) WGMn1 (PWMn1) WGMn0 (PWMn0) 13 1 1 0 14 1 1 15 1 1 Note: 14.10.3 Timer/Counter Mode of Operation TOP Update of OCRnx at TOVn Flag Set on 1 (Reserved) – – – 1 0 Fast PWM ICRn TOP TOP 1 1 Fast PWM OCRnA TOP TOP 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions.
ATmega16/32U4 Table 14-6. Clock Select Bit Description CSn2 CSn1 CSn0 Description 0 0 0 No clock source. (Timer/Counter stopped) 0 0 1 clkI/O/1 (No prescaling 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on Tn pin. Clock on falling edge 1 1 1 External clock source on Tn pin.
ATmega16/32U4 14.10.7 Timer/Counter1 – TCNT1H and TCNT1L Bit 7 6 5 4 3 2 1 0 TCNT1[15:8] TCNT1H TCNT1[7:0] 14.10.
ATmega16/32U4 14.10.12 Output Compare Register 3 A – OCR3AH and OCR3AL Bit 7 6 5 4 3 2 1 0 OCR3A[15:8] OCR3AH OCR3A[7:0] OCR3AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 3 2 1 0 14.10.13 Output Compare Register 3 B – OCR3BH and OCR3BL Bit 7 6 5 4 OCR3B[15:8] OCR3BH OCR3B[7:0] OCR3BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 3 2 1 0 14.10.
ATmega16/32U4 14.10.17 Timer/Counter1 Interrupt Mask Register – TIMSK1 Bit 7 6 5 4 3 2 1 0 – – ICIE1 – OCIE1C OCIE1B OCIE1A TOIE1 Read/Write R R R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK1 14.10.
ATmega16/32U4 14.10.20 Timer/Counter3 Interrupt Flag Register – TIFR3 Bit 7 6 5 4 3 2 1 0 – – ICF3 – OCF3C OCF3B OCF3A TOV3 Read/Write R R R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR3 • Bit 5 – ICFn: Timer/Countern, Input Capture Flag This flag is set when a capture event occurs on the ICPn pin. When the Input Capture Register (ICRn) is set by the WGMn3:0 to be used as the TOP value, the ICFn Flag is set when the counter reaches the TOP value.
ATmega16/32U4 15. 10-bit High Speed Timer/Counter4 15.1 Features • • • • • • • • • • • 15.
ATmega16/32U4 Figure 15-1.
ATmega16/32U4 15.2.3 Registers The Timer/Counter (TCNT4) and Output Compare Registers (OCR4A, OCR4B, OCR4C and OCR4D) are 8-bit registers that are used as a data source to be compared with the TCNT4 contents. The OCR4A, OCR4B and OCR4D registers determine the action on the OC4A, OC4B and OC4D pins and they can also generate the compare match interrupts. The OCR4C holds the Timer/Counter TOP value, i.e. the clear on compare match value.
ATmega16/32U4 Figure 15-2. Timer/Counter4 Synchronization Register Block Diagram.
ATmega16/32U4 15.3 Counter Unit The main part of the Timer/Counter4 is the programmable bi-directional counter unit. Figure 153 shows a block diagram of the counter and its surroundings. Figure 15-3. Counter Unit Block Diagram DATA BUS TOV4 clkT4 Timer/Counter4 Count Enable ( From Prescaler ) count TCNT4 clear Control Logic direction PLLTM1:0 PCK CK bottom top Signal description (internal signals): count TCNT4 increment or decrement enable. direction Select between increment and decrement.
ATmega16/32U4 15.4 Output Compare Unit The comparator continuously compares TCNT4 with the Output Compare Registers (OCR4A, OCR4B, OCR4C and OCR4D). Whenever TCNT4 equals to the Output Compare Register, the comparator signals a match. A match will set the Output Compare Flag (OCF4A, OCF4B or OCF4D) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt.
ATmega16/32U4 Figure 15-5. Effects of Unsynchronized OCR Latching Compare Value changes Counter Value Compare Value Output Compare Waveform OCWnx Synchronized WFnx Latch Compare Value changes Counter Value Compare Value Unsynchronized WFnx Latch Glitch Output Compare Wafeform OCWnx 15.4.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC4x) bit.
ATmega16/32U4 15.5 Dead Time Generator The Dead Time Generator is provided for the Timer/Counter4 PWM output pairs to allow driving external power control switches safely. The Dead Time Generator is a separate block that can be used to insert dead times (non-overlapping times) for the Timer/Counter4 complementary output pairs OC4x and OC4x when the PWM mode is enabled and the COM4x1:0 bits are set to “01”.
ATmega16/32U4 The length of the counting period is user adjustable by selecting the dead time prescaler setting by using the DTPS41:40 control bits, and selecting then the dead time value in I/O register DT4. The DT4 register consists of two 4-bit fields, DT4H and DT4L that control the dead time periods of the PWM output and its' complementary output separately in terms of the number of prescaled dead time generator clock cycles.
ATmega16/32U4 Figure 15-9.
ATmega16/32U4 15.6.2 Enhanced Compare/PWM mode When the bit ENHC4 of TCCR4E register is set, the Enhanced Compare/PWM mode is enabled. This mode allows user to add an accuracy bit to Output Compare Register OCR4A, OCR4B and OCR4D. Like explained previously, a compare condition appears when one of the three Output Compare Registers (OCR4A/B/D) matches the value of TCNT4 (10-bits resolution). In basic PWM Mode, the corresponding enabled output toggles on the Compare Match.
ATmega16/32U4 – Setting OCR4A = 0x85 (= b’10000101’) signifies that the true value of “Compare A” register is 0x42 (b’01000010’) and that the Enhanced bit is set. That means that the duty cycle obtained (51.95%) will be the intermediate value between duty cycles that can be obtained by 0x42 and 0x43 Compare values (51.56%, 52.34%). 15.
ATmega16/32U4 Waveform Output is cleared on the Compare Match. In inverting Compare Output Mode the Waveform Output is set on Compare Match. The timing diagram for the Normal mode is shown in Figure 15-12. The counter value (TCNT4) that is shown as a histogram in the timing diagram is incremented until the counter value matches the TOP value. The counter is then cleared at the following clock cycle The diagram includes the Waveform Output (OCW4x) in toggle Compare Mode.
ATmega16/32U4 The Output Compare Pin configurations in Normal Mode are described in Table 15-2. Table 15-2. 15.8.2 Output Compare Pin Configurations in Normal Mode COM4x1 COM4x0 OC4x Pin OC4x Pin 0 0 Disconnected Disconnected 0 1 Disconnected OC4x 1 0 Disconnected OC4x 1 1 Disconnected OC4x Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (PWM4x = 1 and WGM40 = 0) provides a high frequency PWM waveform generation option.
ATmega16/32U4 The Timer/Counter Overflow Flag (TOV4) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value.4In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC4x pins. Setting the COM4x1:0 bits to two will produce a non-inverted PWM and setting the COM4x1:0 to three will produce an inverted PWM output.
ATmega16/32U4 Match between TCNT4 and OCR4x while upcounting, and set on the Compare Match while down-counting. In inverting Output Compare mode, the operation is inverted. In complementary Compare Output Mode, the Waveform Output is cleared on the Compare Match and set at BOTTOM. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications.
ATmega16/32U4 The N variable represents the number of steps in dual-slope operation. The value of N equals to the TOP value. The extreme values for the OCR4C Register represent special cases when generating a PWM waveform output in the Phase and Frequency Correct PWM mode. If the OCR4C is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
ATmega16/32U4 counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The TCNT4 value is in the timing diagram shown as a histogram for illustrating the singleslope operation. The timing diagram includes Output Compare pins OC4A and OC4A, and the corresponding Output Compare Override Enable bits (OC4OE1..OC4OE0). Figure 15-15.
ATmega16/32U4 Table 15-5. 15.
ATmega16/32U4 Figure 15-18. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclkT4/8) clkPCK clkTn (clkPCK /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 15-19. Timer/Counter Timing Diagram, with Prescaler (fclkT4/8) clkPCK clkTn (clkPCK /8) TCNTn BOTTOM + 1 BOTTOM + 1 BOTTOM BOTTOM + 1 TOVn 15.
ATmega16/32U4 15.10.1 Fault Protection Trigger Source The main trigger source for the Fault Protection unit is the external interrupt pin (INT0). Alternatively the Analog Comparator output can be used as trigger source for the Fault Protection unit. The Analog Comparator is selected as trigger source by setting the Fault Protection Analog Comparator (FPAC4) bit in the Timer/Counter4 Control Register (TCCR4D). Be aware that changing trigger source can trigger a Fault Protection mode.
ATmega16/32U4 15.11 Accessing 10-Bit Registers If 10-bit values are written to the TCNTn and OCRnA/B/C/D registers, the 10-bit registers can be byte accessed by the AVR CPU via the 8-bit data bus using two read or write operations. The 10-bit registers have a common 2-bit Timer/Counter4 High Byte Register (TC4H) that is used for temporary storing of the two MSBs of the 10-bit access. The same TC4H register is shared between all 10-bit registers.
ATmega16/32U4 It is important to notice that accessing 10-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 10-bit register, and the interrupt code updates the TC4H register by accessing the same or any other of the 10-bit timer registers, then the result of the access outside the interrupt will be corrupted.
ATmega16/32U4 The following code examples show how to do an atomic write of the TCNTn register contents. Writing any of the OCRnA/B/C/D registers can be done by using the same principle.
ATmega16/32U4 15.12 Register Description 15.12.1 TCCR4A – Timer/Counter4 Control Register A Bit 7 6 5 4 3 2 1 0 COM4A1 COM4A0 COM4B1 COM4B0 FOC4A FOC4B PWM4A PWM4B Read/Write R/W R/W R/W R/W W W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCCR4A • Bits 7,6 - COM4A1, COM4A0: Comparator A Output Mode, Bits 1 and 0 These bits control the behavior of the Waveform Output (OCW4A) and the connection of the Output Compare pin (OC4A).
ATmega16/32U4 Table 15-8 shows the COM4A1:0 bit functionality when the PWM4A, WGM40 and WGM41 bits are set to Phase and Frequency Correct PWM Mode. Table 15-8. COM1A1..0 Compare Output Mode, Phase and Frequency Correct PWM Mode OCW1A Behavior OC4A Pin OC4A Pin Disconnected Disconnected 00 Normal port operation. 01 Cleared on Compare Match when up-counting. Set on Compare Match when down-counting. Connected Connected 10 Cleared on Compare Match when up-counting.
ATmega16/32U4 that the Data Direction Register (DDR) bit corresponding to the OC4B pin must be set in order to enable the output driver. The function of the COM4B1:0 bits depends on the PWM4B and WGM40 bit settings. Table 1511 shows the COM4B1:0 bit functionality when the PWM4B bit is set to Normal Mode (nonPWM). Table 15-11. Compare Output Mode, Normal Mode (non-PWM) COM4B1..0 OCW4B Behavior OC4B Pin OC4B Pin Disconnected Disconnected 00 Normal port operation. 01 Toggle on Compare Match.
ATmega16/32U4 value. The automatic action programmed in COM4A1 and COM4A0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC4A bit is always read as zero. • Bit 2 - FOC4B: Force Output Compare Match 4B The FOC4B bit is only active when the PWM4B bit specify a non-PWM mode. Writing a logical one to this bit forces a change in the Waveform Output (OCW4B) and the Output Compare pin (OC4B) according to the values already set in COM4B1 and COM4B0.
ATmega16/32U4 Table 15-14. Division factors of the Dead Time prescaler DTPS41 DTPS40 Prescaler divides the T/C4 clock by 0 0 1x (no division) 0 1 2x 1 0 4x 1 1 8x • Bits 3 .. 0 - CS43, CS42, CS41, CS40: Clock Select Bits 3, 2, 1, and 0 The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter4. Table 15-15.
ATmega16/32U4 • Bits 5,4 - COM4B1S, COM4B0S: Comparator B Output Mode, Bits 1 and 0 These bits are the shadow bits of the COM4A1 and COM4A0 bits that are described in the section “TCCR4A – Timer/Counter4 Control Register A” on page 162. • Bits 3,2 - COM4D1, COM4D0: Comparator D Output Mode, Bits 1 and 0 These bits control the behavior of the Waveform Output (OCW4D) and the connection of the Output Compare pin (OC4D).
ATmega16/32U4 Table 15-18. Compare Output Mode, Phase and Frequency Correct PWM Mode COM4D1..0 OCW4D Behavior OC4D Pin OC4D Pin Disconnected Disconnected 00 Normal port operation. 01 Cleared on Compare Match when up-counting. Set on Compare Match when down-counting. Connected Connected 10 Cleared on Compare Match when up-counting. Set on Compare Match when down-counting. Connected Disconnected 11 Set on Compare Match when up-counting. Cleared on Compare Match when down-counting.
ATmega16/32U4 • Bit 3 - FPAC4: Fault Protection Analog Comparator Enable When written logic one, this bit enables the Fault Protection function in Timer/Counter4 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the Fault Protection front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter4 Fault Protection interrupt.
ATmega16/32U4 • Bit 6- ENHC4: Enhanced Compare/PWM Mode When this bit is set, the Waveform Generation Module works in enhanced mode: the compare registers OCR4A/B/D can welcome one more accuracy bit, while the LSB determines on which clock edge the Compare condition is signalled and the output pin level is updated.
ATmega16/32U4 • Bits 1:0 - TC49, TC48: Two MSB bits of the 10-bit accesses If 10-bit accuracy is used, the Timer/Counter4 High Byte Register (TC4H) is used for temporary storing the MSB bits (TC49, TC48) of the 10-bit accesses. The same TC4H register is shared between all 10-bit registers within the Timer/Counter4. Note that special procedures must be followed when accessing the 10-bit TCNT4 register via the 8-bit AVR data bus.
ATmega16/32U4 The output compare register C is an 8-bit read/write register. The Timer/Counter Output Compare Register C contains data to be continuously compared with Timer/Counter4, and a compare match will clear TCNT4. This register has the same function in Normal mode and PWM modes. Note that, if a smaller value than three is written to the Output Compare Register C, the value is automatically replaced by three as it is a minimum value allowed to be written to this register.
ATmega16/32U4 • Bit 5 - OCIE4B: Timer/Counter4 Output Compare Interrupt Enable When the OCIE4B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter4 Compare Match B interrupt is enabled. The corresponding interrupt at vector $009 is executed if a compare match B occurs. The Compare Flag in Timer/Counter4 is set (one) in the Timer/Counter Interrupt Flag Register.
ATmega16/32U4 15.12.14 DT4 – Timer/Counter4 Dead Time Value Bit 7 6 5 4 3 2 1 0 DT4H3 DT4H2 DT4H1 DT4H0 DT4L3 DT4L2 DT4L1 DT4L0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 DT4 The dead time value register is an 8-bit read/write register. The dead time delay of all Timer/Counter4 channels are adjusted by the dead time value register, DT4. The register consists of two fields, DT4H3..0 and DT4L3..0, one for each complementary output.
ATmega16/32U4 16. Output Compare Modulator (OCM1C0A) 16.1 Overview The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter0. For more details about these Timer/Counters see “Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers” on page 89. Figure 16-1.
ATmega16/32U4 When the modulator is enabled the type of modulation (logical AND or OR) can be selected by the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the COMnx1:0 bit setting. 16.2.1 Timing Example Figure 16-3 illustrates the modulator in action. In this example the Timer/Counter1 is set to operate in fast PWM mode (non-inverted) and Timer/Counter0 uses CTC waveform mode with toggle Compare Output mode (COMnx1:0 = 1). Figure 16-3.
ATmega16/32U4 17. Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega16U4/ATmega32U4 and peripheral devices or between several AVR devices.
ATmega16/32U4 communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line.
ATmega16/32U4 When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 17-1. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 70. Table 17-1. Pin SPI Pin Overrides(1) Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1.
ATmega16/32U4 Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<
ATmega16/32U4 The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
ATmega16/32U4 other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic, and drop any partially received data in the Shift Register.
ATmega16/32U4 and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 17-3 and Figure 17-4 for an example. The CPOL functionality is summarized below: Table 17-2.
ATmega16/32U4 • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector.
ATmega16/32U4 Table 17-5. CPOL Functionality Leading Edge Trailing eDge SPI Mode CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 0 CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) 1 CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 2 CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) 3 Figure 17-3.
ATmega16/32U4 18. USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device.
ATmega16/32U4 Figure 18-1. USART Block Diagram(1) Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATA BUS PARITY GENERATOR TxD Receiver UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRB RxD UCSRC 1. See “Pinout ATmega16U4/ATmega32U4” on page 3, Table 10-8 on page 77 and for USART pin placement.
ATmega16/32U4 UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only active when using synchronous mode. Figure 18-2 shows a block diagram of the clock generation logic. Figure 18-2.
ATmega16/32U4 Table 18-1 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRRn value for each mode of operation using an internally generated clock source. Table 18-1.
ATmega16/32U4 18.2.3 External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to Figure 18-2 for details. External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and Receiver.
ATmega16/32U4 A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. Figure 18-4 illustrates the possible combinations of the frame formats.
ATmega16/32U4 18.4 USART Initialization The USART has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the initialization.
ATmega16/32U4 18.5 Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overridden by the USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions.
ATmega16/32U4 18.5.2 Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in UCSRnB before the low byte of the character is written to UDRn. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
ATmega16/32U4 When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that global interrupts are enabled). UDREn is cleared by writing UDRn.
ATmega16/32U4 bits of the data read from the UDRn will be masked to zero. The USART has to be initialized before the function can be used. Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get and return received data from buffer in r16, UDRn ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSRnA & (1<
ATmega16/32U4 Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer in r18, UCSRnA in r17, UCSRnB in r16, UDRn ; If error, return -1 andi r18,(1<
ATmega16/32U4 18.6.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero.
ATmega16/32U4 The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 18.6.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e.
ATmega16/32U4 Figure 18-5. Start Bit Sampling RxD IDLE START BIT 0 Sample (U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (U2X = 1) 0 1 2 3 4 5 6 7 8 1 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure.
ATmega16/32U4 Figure 18-7. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample (U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample (U2X = 1) 1 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
ATmega16/32U4 Table 18-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ± 3.0 6 94.12 105.79 +5.79/-5.88 ± 2.5 7 94.81 105.11 +5.11/-5.19 ± 2.0 8 95.36 104.58 +4.58/-4.54 ± 2.0 9 95.81 104.14 +4.14/-4.19 ± 1.5 10 96.17 103.78 +3.78/-3.83 ± 1.5 Table 18-3.
ATmega16/32U4 nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed.
ATmega16/32U4 18.9.1 Receiver Flow Control The reception flow can be controlled by hardware using the RTS pin. The aim of the flow control is to inform the external transmitter when the internal receive Fifo is full. Thus the transmitter can stop sending characters. RTS usage and so associated flow control is enabled using RTSEN bit in UCSRnD. Figure 18-8. shows a reception example. Figure 18-8. Reception Flow Control Waveform Example FIFO Index 0 1 2 1 0 1 CPU Read C1 C2 RXD C3 RTS Figure 18-9.
ATmega16/32U4 18.10 USART Register Description 18.10.1 USART I/O Data Register n– UDRn Bit 7 6 5 4 3 2 1 0 RXB[7:0] UDRn (Read) TXB[7:0] UDRn (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn.
ATmega16/32U4 • Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRnA. • Bit 3 – DORn: Data OverRun This bit is set if a Data OverRun condition is detected.
ATmega16/32U4 • Bit 4 – RXENn: Receiver Enable n Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FEn, DORn, and UPEn Flags. • Bit 3 – TXENn: Transmitter Enable n Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxDn pin when enabled.
ATmega16/32U4 Receiver will generate a parity value for the incoming data and compare it to the UPMn setting. If a mismatch is detected, the UPEn Flag in UCSRnA will be set. Table 18-5. UPMn Bit Settings UPMn1 UPMn0 Parity Mode 0 0 Disabled 0 1 Reserved 1 0 Enabled, Even Parity 1 1 Enabled, Odd Parity • Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 18-6.
ATmega16/32U4 18.10.5 USART Control and Status Register n D– UCSRnD Bit 7 6 5 – – 4 3 2 – – – – 1 0 CTSEN RTSEN Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 UCSRnD • Bits 7:2 – Reserved bits These bits are reserved and will be read as ‘0’. Do not set these bits. • Bits 1 – CTSEN: UART CTS Signal Enable Set this bit by firmware to enable the transmission flow control signal (CTS). Transmission will be enabled only if CTS input = 0.
ATmega16/32U4 resistance when the error ratings are high, especially for large serial frames (see “Asynchronous Operational Range” on page 201). The error values are calculated using the following equation: BaudRate Closest Match - – 1⎞ • 100% Error[%] = ⎛ ------------------------------------------------------⎝ ⎠ BaudRate Table 18-9. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies fosc = 1.0000 MHz fosc = 1.8432 MHz fosc = 2.0000 MHz Baud Rate (bps) UBRR 2400 25 0.2% 51 0.
ATmega16/32U4 Table 18-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864 MHz Baud Rate (bps) U2Xn = 0 UBRR fosc = 4.0000 MHz U2Xn = 1 Error UBRR U2Xn = 0 Error UBRR fosc = 7.3728 MHz U2Xn = 1 Error UBRR U2Xn = 0 Error UBRR U2Xn = 1 Error UBRR Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.
ATmega16/32U4 Table 18-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592 MHz fosc = 8.0000 MHz fosc = 14.7456 MHz Baud Rate (bps) UBRR 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.2% 35 0.
ATmega16/32U4 Table 18-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz Baud Rate (bps) UBRR 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.2k 51 0.2% 103 0.
ATmega16/32U4 19. USART in SPI Mode The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be set to a master SPI compliant mode of operation. The Master SPI Mode (MSPIM) has the following features: • • • • • • • • 19.
ATmega16/32U4 Note: 19.3 1. The baud rate is defined to be the transfer rate in bit per second (bps) BAUD Baud rate (in bits per second, bps) fOSC System Oscillator clock frequency UBRRn Contents of the UBRRnH and UBRRnL Registers, (0-4095) SPI Data Modes and Timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in Figure 19-1.
ATmega16/32U4 The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. 16-bit data transfer can be achieved by writing two data bytes to UDRn. A UART transmit complete interrupt will then signal that the 16-bit value has been shifted out. 19.4.
ATmega16/32U4 Assembly Code Example(1) USART_Init: clr r18 out UBRRnH,r18 out UBRRnL,r18 ; Setting the XCKn port pin as output, enables master mode. sbi XCKn_DDR, XCKn ; Set MSPI mode of operation and SPI data mode 0. ldi r18, (1<
ATmega16/32U4 After initialization the USART is ready for doing data transfers. A data transfer is initiated by writing to the UDRn I/O location. This is the case for both sending and receiving data since the transmitter controls the transfer clock. The data written to UDRn is moved from the transmit buffer to the shift register when the shift register is ready to send a new frame.
ATmega16/32U4 Note: 1. See “Code Examples” on page 8. 19.5.1 Transmitter and Receiver Flags and Interrupts The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode are identical in function to the normal USART operation. However, the receiver error status flags (FE, DOR, and PE) are not in use and is always read as zero. 19.5.
ATmega16/32U4 19.6.3 USART MSPIM Control and Status Register n B - UCSRnB Bit 7 6 5 4 3 2 1 0 RXCIEn TXCIEn UDRIE RXENn TXENn - - - Read/Write R/W R/W R/W R/W R/W R R R Initial Value 0 0 0 0 0 1 1 0 UCSRnB • Bit 7 - RXCIEn: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXCn Flag.
ATmega16/32U4 • Bit 7:6 - UMSELn1:0: USART Mode Select These bits select the mode of operation of the USART as shown in Table 19-3. See “USART Control and Status Register n C – UCSRnC” on page 207 for full description of the normal USART operation. The MSPIM is enabled when both UMSELn bits are set to one. The UDORDn, UCPHAn, and UCPOLn can be set in the same write operation where the MSPIM is enabled. Table 19-3.
ATmega16/32U4 • The USART in MSPIM mode includes (double) buffering of the transmitter. The SPI has no buffer. • The USART in MSPIM mode receiver includes an additional buffer level. • The SPI WCOL (Write Collision) bit is not included in USART in MSPIM mode. • The SPI double speed mode (SPI2X) bit is not included. However, the same effect is achieved by setting UBRRn accordingly. • Interrupt timing is not compatible. • Pin control differs due to the master only operation of the USART in MSPIM mode.
ATmega16/32U4 20. 2-wire Serial Interface 20.1 Features • • • • • • • • • • 20.
ATmega16/32U4 The Power Reduction TWI bit, PRTWI bit in “Power Reduction Register 0 - PRR0” on page 46 must be written to zero to enable the 2-wire Serial Interface. 20.2.2 Electrical Interconnection As depicted in Figure 20-1, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface.
ATmega16/32U4 depicted below, START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high. Figure 20-3. START, REPEATED START and STOP conditions SDA SCL STOP START 20.3.3 START REPEATED START STOP Address Packet Format All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit.
ATmega16/32U4 20.3.4 Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and the START and STOP conditions, while the Receiver is responsible for acknowledging the reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signalled.
ATmega16/32U4 20.4 Multi-master Bus Systems, Arbitration and Synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems arise in multi-master systems: • An algorithm must be implemented allowing only one of the masters to complete the transmission.
ATmega16/32U4 bits. If several masters are trying to address the same Slave, arbitration will continue into the data packet. Figure 20-8. Arbitration Between Two Masters START SDA from Master A Master A Loses Arbitration, SDAA SDA SDA from Master B SDA Line Synchronized SCL Line Note that arbitration is not allowed between: • A REPEATED START condition and a data bit. • A STOP condition and a data bit. • A REPEATED START and a STOP condition.
ATmega16/32U4 Figure 20-9. Overview of the TWI Module Slew-rate Control SDA Spike Filter Slew-rate Control Spike Filter Bus Interface Unit START / STOP Control Spike Suppression Arbitration detection Address/Data Shift Register (TWDR) Address Match Unit Address Register (TWAR) Address Comparator Bit Rate Generator Prescaler Bit Rate Register (TWBR) Ack Control Unit Status Register (TWSR) Control Register (TWCR) State Machine and Status control TWI Unit SCL 20.5.
ATmega16/32U4 CPU Clock frequency SCL frequency = ----------------------------------------------------------TWPS 16 + 2(TWBR) ⋅ 4 • TWBR = Value of the TWI Bit Rate Register. • TWPS = Value of the prescaler bits in the TWI Status Register. Note: 20.5.3 TWBR should be 10 or higher if the TWI operates in Master mode. If TWBR is lower than 10, the Master may produce an incorrect output on SDA and SCL for the reminder of the byte.
ATmega16/32U4 The TWINT Flag is set in the following situations: • After the TWI has transmitted a START/REPEATED START condition. • After the TWI has transmitted SLA+R/W. • After the TWI has transmitted an address byte. • After the TWI has lost arbitration. • After the TWI has been addressed by own slave address or general call. • After the TWI has received a data byte. • After a STOP or REPEATED START has been received while still addressed as a Slave.
ATmega16/32U4 1. The device’s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in Master Receiver or Slave Receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again.
ATmega16/32U4 caler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. • Bit 2 – Res: Reserved Bit This bit is reserved and will always read as zero. • Bits 1..0 – TWPS: TWI Prescaler Bits These bits can be read and written, and control the bit rate prescaler. Table 20-2.
ATmega16/32U4 The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is generated. • Bits 7..1 – TWA: TWI (Slave) Address Register These seven bits constitute the slave address of the TWI unit.
ATmega16/32U4 state of the TWI bus. The application software can then decide how the TWI should behave in the next TWI bus cycle by manipulating the TWCR and TWDR Registers. Figure 20-11 is a simple example of how the application can interface to the TWI hardware. In this example, a Master wishes to transmit a single data byte to a Slave. This description is quite abstract, a more detailed explanation follows later in this section. A simple code example implementing the desired behavior is also presented.
ATmega16/32U4 5. The application software should now examine the value of TWSR, to make sure that the address packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must load a data packet into TWDR.
ATmega16/32U4 Assembly Code Example ldi r16, (1<
ATmega16/32U4 20.8 Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used.
ATmega16/32U4 Figure 20-12. Data Transfer in Master Transmitter Mode VCC Device 1 Device 2 MASTER TRANSMITTER SLAVE RECEIVER Device 3 ........ Device n R1 R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 1 X 1 0 X 1 0 X TWEN must be set to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be written to one to clear the TWINT Flag.
ATmega16/32U4 After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus. Table 20-3.
ATmega16/32U4 Figure 20-13.
ATmega16/32U4 Figure 20-14. Data Transfer in Master Receiver Mode VCC Device 1 Device 2 MASTER RECEIVER SLAVE TRANSMITTER Device 3 ........ Device n R1 R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 1 X 1 0 X 1 0 X TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT Flag.
ATmega16/32U4 the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus. Table 20-4.
ATmega16/32U4 Figure 20-15.
ATmega16/32U4 The upper 7 bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgement of the device’s own slave address or the general call address.
ATmega16/32U4 Table 20-5.
ATmega16/32U4 Figure 20-17. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
ATmega16/32U4 To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 value TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Device’s Own Slave Address The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.
ATmega16/32U4 Table 20-6.
ATmega16/32U4 Figure 20-19. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes S SLA R A DATA $A8 Arbitration lost as master and addressed as slave A DATA $B8 A P or S $C0 A $B0 Last data byte transmitted. Switched to not addressed slave (TWEA = '0') A All 1's P or S $C8 DATA From master to slave From slave to master 20.8.
ATmega16/32U4 Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must be changed. The Master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation.
ATmega16/32U4 • Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are being addressed by the winning Master. If addressed, they will switch to SR or ST mode, depending on the value of the READ/WRITE bit.
ATmega16/32U4 21. USB controller 21.1 Features • • • • Supports full-speed and low-speed Device role Complies with USB Specification v2.0 Supports ping-pong mode (dual bank) 832 bytes of DPRAM: – 1 endpoint 64 bytes max (default control endpoint) – 1 endpoints of 256 bytes max, (one or two banks) – 5 endpoints of 64 bytes max, (one or two banks) • Crystal-less operation for low-speed mode 21.
ATmega16/32U4 21.3 Typical Application Implementation Depending on the target application power supply, the ATmega16U4/ATmega32U4 requires different hardware typical implementations. Figure 21-2. Operating modes versus frequency and power-supply Max Operating Frequency (MHz) VCC (V) 5.5 16 MHz 4.5 USB compliant, with internal regulator 3.6 8 MHz 3.4 USB compliant, without internal regulator 3.0 2.7 USB not operational 2 MHz VCC min 0 21.3.1 Bus Powered device Figure 21-3.
ATmega16/32U4 Figure 21-4. Typical Bus powered application with 3V I/O External 3V Regulator UVCC AVCC VCC UCAP 1µF VBUS VBUS UDP D+ Rs=22 UDM DRs=22 UVSS UVSS UGND UID UID XTAL1 21.3.2 XTAL2 GND GND Self Powered device Figure 21-5. Typical Self powered application with 3.4V to 5.5V I/O External 3.4V - 5.
ATmega16/32U4 Figure 21-6. Typical Self powered application with 3.0V to 3.6 I/O External 3.0V - 3.6V Power Supply UVCC AVCC VCC UCAP 1µF VBUS VBUS UDP D+ Rs=22 UDM DRs=22 UVSS UID UGND UID XTAL1 21.4 XTAL2 GND GND Crystal-less operation To reduce external components count and BOM cost, the USB module can be configured to operate in low-speed mode with internal RC oscillator as input source clock for the PLL.
ATmega16/32U4 21.6 21.6.1 General Operating Modes Introduction The USB controller is disabled and reset after an hardware reset generated by: – Power on reset – External reset – Watchdog reset – Brown out reset – JTAG reset But another available and optional CPU reset source is: – USB End Of Reset In this case, the USB controller is reset, but not disabled (so that the device remains attached). 21.6.2 Power-on and reset The next diagram explains the USB controller main states on power-on: Figure 21-7.
ATmega16/32U4 Figure 21-8. USB Interrupt System USB General Interrupt USB General Interrupt Vector USB Device Interrupt USB Endpoint/Pipe Interrupt Vector Endpoint Interrupt The USB hardware module distinguishes between USB General events and USB Endpoint events that are relevant with data transfers relative to each endpoint. Figure 21-9. USB General interrupt vector sources VBUSTI USBINT.0 UPRSMI UDINT.6 EORSMI UDINT.5 USB General Interrupt Vector VBUSTE USBCON.0 UPRSME UDIEN.6 EORSME UDIEN.
ATmega16/32U4 Figure 21-10. USB Endpoint Interrupt vector sources Endpoint 6 Endpoint 5 Endpoint 4 Endpoint 3 Endpoint 2 Endpoint 1 Endpoint 0 OVERFI UESTAX.6 UNDERFI UESTAX.5 NAKINI UEINTX.6 NAKOUTI UEINTX.4 RXSTPI UEINTX.3 RXOUTI UEINTX.2 FLERRE UEIENX.7 NAKINE UEIENX.6 TXSTPE UEIENX.4 RXSTPE UEIENX.3 EPINT UEINT.X USB Endpoint Interrupt Vector RXOUTE UEIENX.2 STALLEDI UEINTX.1 STALLEDE UEIENX.1 TXINI UEINTX.0 TXINE UEIENX.
ATmega16/32U4 21.7.3 Freeze clock The firmware has the ability to reduce the power consumption by setting the FRZCLK bit, which freeze the clock of USB controller. When FRZCLK is set, it is still possible to access to the following registers: • USBCON, USBSTA, USBINT • UDCON (detach, ...) • UDINT • UDIEN Moreover, when FRZCLK is set, only the following interrupts may be triggered: • WAKEUPI • VBUSTI 21.8 Speed Control The speed selection (Full Speed or Low Speed) depends on the D+/D- pull-up.
ATmega16/32U4 The following figure illustrates the allocation and reorganization of the USB memory in a typical example: Table 21-1.
ATmega16/32U4 Figure 21-12. Pad behaviour USBE=1 & DETACH=0 & suspend Idle mode USBE=0 | DETACH=1 | suspend Active mode The SUSPI flag indicated that a suspend state has been detected on the USB bus. This flag automatically put the USB pad in Idle. The detection of a non-idle event sets the WAKEUPI flag and wakes-up the USB pad.
ATmega16/32U4 Figure 21-13. Plug-in Detection Input Block Diagram RPU VDD Session_valid VBUS VBUSTI USBSTA.0 USBINT.0 RPU VBUS VSS Pad logic The control logic of the VBUS pad outputs a signal regarding the VBUS voltage level: • The “Session_valid” signal is active high when the voltage on the UVBUS pad is higher or equal to 1.4V. If lower than 1.4V, the signal is not active. • The VBUS status bit is set when “Session_valid” signal is active (VBUS > 1.4V).
ATmega16/32U4 • 5 – FRZCLK: Freeze USB Clock Bit Set to disable the clock inputs (the ”Resume Detection” is still active). This reduces the power consumption. Clear to enable the clock inputs. • 4 – OTGPADE: VBUS Pad Enable Set to enable the VBUS pad. Clear to disable the VBUS pad. Note that this bit can be set/cleared even if USBE=0. That allows the VBUS detection even if the USB macro is disable. • 3-1 – Reserved The value read from these bits is always 0. Do not set these bits.
ATmega16/32U4 21.13 USB Software Operating modes Depending on the USB operating mode, the software should perform some the following operations: Power On the USB interface • Power-On USB pads regulator • Configure PLL interface • Enable PLL • Check PLL lock • Enable USB interface • Configure USB interface (USB speed, Endpoints configuration...
ATmega16/32U4 22. USB Device Operating modes 22.1 Introduction The USB device controller supports full speed and low speed data transfers. In addition to the default control endpoint, it provides six other endpoints, which can be configured in control, bulk, interrupt or isochronous modes: • Endpoint 0:programmable size FIFO up to 64 bytes, default control endpoint • Endpoints 1 programmable size FIFO up to 256 bytes in ping-pong mode.
ATmega16/32U4 • the UEINTX, UESTA0X and UESTA1X are restored to their reset value. The data toggle field remains unchanged. The other registers remain unchanged. The endpoint configuration remains active and the endpoint is still enabled. The endpoint reset may be associated with a clear of the data toggle command (RSTDT bit) as an answer to the CLEAR_FEATURE USB command. 22.4 USB reset When an USB reset is detected on the USB line (SE0 state with a minimum duration of 2.
ATmega16/32U4 Figure 22-2. Endpoint activation flow: Endpoint Activation UENUM Select the endpoint EPNUM=x EPEN=1 Activate the endpoint UECFG0X Configure: - the endpoint direction - the endpoint type EPDIR EPTYPE ...
ATmega16/32U4 ADDEN is cleared by hardware: • after a power-up reset, • when an USB reset is received, • or when the macro is disabled (USBE cleared) When this bit is cleared, the default device address 00h is used. 22.8 Suspend, Wake-up and Resume After a period of 3 ms during which the USB line was inactive, the controller switches to the fullspeed mode and triggers (if enabled) the SUSPI (suspend) interrupt. The firmware may then set the FRZCLK bit.
ATmega16/32U4 22.10 Remote Wake-up The “Remote Wake-up” (or “upstream resume”) feature is the only operation allowed to be sent by the device on its own initiative. Anyway, to do that, the device should first have received a DEVICE_REMOTE_WAKEUP request from the host. • First, the USB controller must have detected the “suspend” state of the line: the remote wakeup can only be sent when a SUSPI flag is set. • The firmware has then the ability to set RMWKUP to send the “upstream resume” stream.
ATmega16/32U4 22.11.2 STALL handshake and Retry mechanism The Retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the STALLRQ request bit is set and if there is no retry required. 22.12 CONTROL endpoint management A SETUP request is always ACK’ed. When a new setup packet is received, the RXSTPI interrupt is triggered (if enabled). The RXOUTI interrupt is not triggered. The FIFOCON and RWAL fields are irrelevant with CONTROL endpoints.
ATmega16/32U4 22.12.2 Control Read The next figure shows a control read transaction. The USB controller has to manage the simultaneous write requests from the CPU and the USB host: SETUP USB line DATA SETUP RXSTPI HW IN STATUS IN OUT OUT NAK SW RXOUTI TXINI HW SW HW SW SW Wr Enable HOST Wr Enable CPU A NAK handshake is always generated at the first status stage command.
ATmega16/32U4 switch to the next bank. The RXOUTI and FIFOCON bits are then updated by hardware in accordance with the status of the new bank. RXOUTI shall always be cleared before clearing FIFOCON. The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can read data from the bank, and cleared by hardware when the bank is empty.
ATmega16/32U4 22.14 IN endpoint management IN packets are sent by the USB device controller, upon an IN request from the host. All the data can be written by the CPU, which acknowledge or not the bank when it is full.Overview The Endpoint must be configured first. The TXINI bit is set by hardware when the current bank becomes free. This triggers an interrupt if the TXINE bit is set. The FIFOCON bit is set at the same time.
ATmega16/32U4 • after “N” write into UEDATX • as soon as RWAL is cleared by hardware. If the endpoint uses 2 banks, the second one can be read by the HOST while the current is being written by the CPU. Then, when the CPU clears FIFOCON, the next bank may be already ready (free) and TXINI is set immediately. 22.14.1.
ATmega16/32U4 22.15.2 CRC Error A CRC error can occur during OUT stage if the USB controller detects a bad received packet. In this situation, the STALLEDI interrupt is triggered. This does not prevent the RXOUTI interrupt from being triggered. 22.16 Overflow In Control, Isochronous, Bulk or Interrupt Endpoint, an overflow can occur during OUT stage, if the host attempts to write in a bank that is too small for the packet. In this situation, the OVERFI interrupt is triggered (if enabled).
ATmega16/32U4 Figure 22-5. USB Device Controller Endpoint Interrupt System Endpoint 6 Endpoint 5 Endpoint 4 Endpoint 3 Endpoint 2 Endpoint 1 Endpoint 0 OVERFI UESTAX.6 UNDERFI UESTAX.5 NAKINI UEINTX.6 NAKOUTI UEINTX.4 RXSTPI UEINTX.3 RXOUTI UEINTX.2 FLERRE UEIENX.7 NAKINE UEIENX.6 TXSTPE UEIENX.4 Endpoint Interrupt EPINT UEINT.X TXOUTE UEIENX.3 RXOUTE UEIENX.2 STALLEDI UEINTX.1 STALLEDE UEIENX.1 TXINI UEINTX.0 TXINE UEIENX.
ATmega16/32U4 • 7-4 - Reserved The value read from these bits is always 0. Do not set these bits. • 3 - RSTCPU - USB Reset CPU bit Set this bit to 1 by firmware in order to reset the CPU on the detection of a USB End of Reset signal (without disabling the USB controller and Attached state). This bit is reset when the USB controller is disabled, but is not affected by the CPU reset generated after a USB End of Reset (remains enabled).
ATmega16/32U4 • 4 - WAKEUPI - Wake-up CPU Interrupt Flag Set by hardware when the USB controller is re-activated by a filtered non-idle signal from the lines (not by an upstream resume). This triggers an interrupt if WAKEUPE is set. Shall be cleared by software (USB clock inputs must be enabled before). Setting by software has no effect. See Section 22.8, page 269 for more details. • 3 - EORSTI - End Of Reset Interrupt Flag Set by hardware when an “End Of Reset” has been detected by the USB controller.
ATmega16/32U4 • 3 - EORSTE - End Of Reset Interrupt Enable Bit Set to enable the EORSTI interrupt. This bit is set after a reset. Clear to disable the EORSTI interrupt. • 2 - SOFE - Start Of Frame Interrupt Enable Bit Set to enable the SOFI interrupt. Clear to disable the SOFI interrupt. • 1 - Reserved The value read from this bits is always 0. Do not set this bit • 0 - SUSPE - Suspend Interrupt Enable Bit Set to enable the SUSPI interrupt. Clear to disable the SUSPI interrupt.
ATmega16/32U4 • Frame Number Lower Value Set by hardware. These bits are the 8 LSB of the 11-bits Frame Number information. Bit 7 6 5 4 3 2 1 0 - - - FNCERR - - - - 0 0 0 0 Read/W rite Initial Value UDMFN R 0 0 0 0 • 7-5 - Reserved The value read from these bits is always 0. Do not set these bits. • 4 - FNCERR -Frame Number CRC Error Flag Set by hardware when a corrupted Frame Number in start of frame packet is received.
ATmega16/32U4 Then, clear by software to complete the reset operation and start using the endpoint. Bit 7 6 5 4 3 2 1 0 - - STALLRQ STALLRQC RSTDT - - EPEN Read/Write R R W W W R R R/W Initial Value 0 0 0 0 0 0 0 0 UECONX • 7-6 - Reserved The value read from these bits is always 0. Do not set these bits. • 5 - STALLRQ - STALL Request Handshake Bit Set to request a STALL answer to the host for the next handshake. Cleared by hardware when a new SETUP is received.
ATmega16/32U4 00b: Control10b: Bulk 01b: Isochronous11b: Interrupt • 5-1 - Reserved The value read from these bits is always 0. Do not set these bits. • 0 - EPDIR - Endpoint Direction Bit Set to configure an IN direction for bulk, interrupt or isochronous endpoints. Clear to configure an OUT direction for bulk, interrupt, isochronous or control endpoints.
ATmega16/32U4 • 7 - CFGOK - Configuration Status Flag Set by hardware when the endpoint X size parameter (EPSIZE) and the bank parametrization (EPBK) are correct compared to the max FIFO capacity and the max number of allowed bank. This bit is updated when the bit ALLOC is set. If this bit is cleared, the user should reprogram the UECFG1X register with correct EPSIZE and EPBK values. • 6 - OVERFI - Overflow Error Interrupt Flag Set by hardware when an overflow error occurs in an isochronous endpoint.
ATmega16/32U4 Bit 7 6 5 4 3 2 - - - - - CTRLDIR 1 0 Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 CURRBK1:0 UESTA1X • 7-3 - Reserved The value read from these bits is always 0. Do not set these bits. • 2 - CTRLDIR - Control Direction (Flag, and bit for debug purpose) Set by hardware after a SETUP packet, and gives the direction of the following packet: - 1 for IN endpoint - 0 for OUT endpoint. Can not be set or cleared by software.
ATmega16/32U4 • 5 - RWAL - Read/Write Allowed Flag Set by hardware to signal: - for an IN endpoint: the current bank is not full i.e. the firmware can push data into the FIFO, - for an OUT endpoint: the current bank is not empty, i.e. the firmware can read data from the FIFO. The bit is never set if STALLRQ is set, or in case of error. Cleared by hardware otherwise. This bit shall not be used for the control endpoint.
ATmega16/32U4 Bit 7 6 5 4 3 2 1 0 FLERRE NAKINE - NAKOUTE RXSTPE RXOUTE STALLEDE TXINE Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 UEIENX • 7 - FLERRE - Flow Error Interrupt Enable Flag Set to enable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are sent. Clear to disable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are sent.
ATmega16/32U4 Bit 7 - 6 - 5 - 4 3 - 2 - 1 0 BYCT D10 BYCT D9 BYCT D8 Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 UEBCHX • 7-3 - Reserved The value read from these bits is always 0. Do not set these bits. • 2-0 - BYCT10:8 - Byte count (high) Bits Set by hardware. This field is the MSB of the byte count of the FIFO endpoint. The LSB part is provided by the UEBCLX register.
ATmega16/32U4 23. Analog Comparator The Analog Comparator compares the input values on the positive pin AIN+ and negative pin AIN-. When the voltage on the positive pin AIN+ is higher than the voltage on the negative pin AIN-, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
ATmega16/32U4 • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
ATmega16/32U4 23.1 Analog Comparator Multiplexed Input It is possible to select any of the ADC13..0 pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), and MUX2..
ATmega16/32U4 24. Analog to Digital Converter - ADC 24.1 Features • • • • • • • • • • • • • • • 10/8-bit Resolution 0.5 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 65 - 260 µs Conversion Time Up to 15 kSPS at Maximum Resolution Twelve Multiplexed Single-Ended Input Channels One Differential amplifier providing gain of 1x - 10x - 40x - 200x Temperature sensor Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 2.
ATmega16/32U4 Figure 24-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[3:0] TRIGGER SELECT ADC[9:0] ADPS1 0 ADC DATA REGISTER (ADCH/ADCL) ADPS0 ADPS2 ADIF ADATE ADEN ADSC MUX0 MUX2 15 ADC CTRL.
ATmega16/32U4 24.2 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity.
ATmega16/32U4 Figure 24-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START CLKADC ADATE ADIF SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA.
ATmega16/32U4 in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. See “Differential Channels” on page 297 for details on differential conversion timing. A normal conversion takes 13 ADC clock cycles.
ATmega16/32U4 Figure 24-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion Cycle Number 1 2 3 4 5 6 7 8 Next Conversion 10 9 11 12 13 1 2 ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Prescaler Reset Sample & Hold Prescaler Reset Conversion Complete MUX and REFS Update Figure 24-7.
ATmega16/32U4 clock cycles due to the synchronization mechanism. In Free Running mode, a new conversion is initiated immediately after the previous conversion completes, and since CKADC2 is high at this time, all automatically started (i.e., all but the first) Free Running conversions will take 14 ADC clock cycles. If differential channels are used and conversions are started by Auto Triggering, the ADC must be switched off between conversions.
ATmega16/32U4 The settling time and gain stage bandwidth is independent of the ADHSM bit setting. 24.5.1 ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: • In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC.
ATmega16/32U4 The temperature sensor and its internal driver are enabled when ADMUX value selects the temperature sensor as ADC input. The propagation delay of this driver is approximatively 2µS. Therefore two successive conversions are required. The correct temperature measurement will be the second one. One can also reduce this timing to one conversion by setting the ADMUX during the previous conversion.
ATmega16/32U4 24.7 ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: a. Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled. b.
ATmega16/32U4 Figure 24-9. Analog Input Circuitry IIH ADCn 1..100 kΩ CS/H= 14 pF IIL VCC/2 24.7.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. Keep analog signal paths as short as possible.
ATmega16/32U4 24.7.3 Offset Compensation Schemes The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible. The remaining offset in the analog path can be measured directly by selecting the same channel for both differential inputs. This offset residue can be then subtracted in software from the measurement results. Using this kind of software based offset correction, offset on any channel can be reduced below one LSB. 24.7.
ATmega16/32U4 Figure 24-12. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 24-13.
ATmega16/32U4 Figure 24-14. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. • Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code.
ATmega16/32U4 Figure 24-15. Differential Measurement Range Output Code 0x1FF 0x000 - VREF 0x3FF 0 VREF Differential Input Voltage (Volts) 0x200 Table 24-2. Correlation Between Input Voltage and Output Codes VADCn Read code Corresponding decimal value VADCm + VREF /GAIN 0x1FF 511 VADCm + 0.999 VREF /GAIN 0x1FF 511 VADCm + 0.998 VREF /GAIN 0x1FE 510 ... ... ... VADCm + 0.001 VREF /GAIN 0x001 1 VADCm 0x000 0 VADCm - 0.001 VREF /GAIN 0x3FF -1 ... ... ... VADCm - 0.
ATmega16/32U4 – ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02. Example 2: – ADMUX = 0xF0, MUX5 = 0 (ADC0 - ADC1, 1x gain, 2.56V reference, left adjusted result) – Voltage on ADC0 is 300 mV, voltage on ADC1 is 500 mV. – ADCR = 512 * 1 * (300 - 500) / 2560 = -41 = 0x029. – ADCL will thus read 0x40, and ADCH will read 0x0A. Writing zero to ADLAR right adjusts the result: ADCL = 0x00, ADCH = 0x29. 24.9 24.9.
ATmega16/32U4 Table 24-4. MUX5..
ATmega16/32U4 Table 24-4. MUX5..
ATmega16/32U4 Table 24-4. MUX5..0(1) Input Channel and Gain Selections (Continued) Single Ended Input Positive Differential Input Negative Differential Input Gain 110100 ADC4 ADC1 40x 110101 ADC5 ADC1 40x 110110 ADC6 ADC1 40x 110111 ADC7 ADC1 40x 111000 ADC4 ADC0 200x ADC5 ADC0 200x 111010 ADC6 ADC0 200x 111011 ADC7 ADC0 200x 111100 ADC4 ADC1 200x 111101 ADC5 ADC1 200x 111110 ADC6 ADC1 200x 111111 ADC7 ADC1 200x 111001 N/A Note: 24.9.2 1.
ATmega16/32U4 Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. • Bit 3 – ADIE: ADC Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated. • Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. Table 24-5. 24.9.3 24.9.3.
ATmega16/32U4 channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. • ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 305. 24.9.
ATmega16/32U4 Table 24-6. 24.9.5 ADC Auto Trigger Source Selections (Continued) ADTS3 ADTS2 ADTS1 ADTS0 Trigger Source 1 0 0 1 Timer/Counter4 Compare Match A 1 0 1 0 Timer/Counter4 Compare Match B 1 0 1 1 Timer/Counter4 Compare Match D Digital Input Disable Register 0 – DIDR0 Bit 7 6 5 4 3 2 1 0 ADC7D ADC6D ADC5D ADC4D - - ADC1D ADC0D Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DIDR0 • Bit 7:4, 1:0 – ADC7D..4D - ADC1D..
ATmega16/32U4 25. JTAG Interface and On-chip Debug System 25.0.1 Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.
ATmega16/32U4 • TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains). • TDO: Test Data Out. Serial output data from Instruction Register or Data Register. The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided. When the JTAGEN Fuse is unprogrammed, these four TAP pins are normal port pins, and the TAP controller is in reset.
ATmega16/32U4 Figure 25-2. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 25.
ATmega16/32U4 • Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine. • At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-DR state.
ATmega16/32U4 • 2 single Program Memory Break Points + 1 Data Memory Break Point with mask (“range Break Point”). A debugger, like the AVR Studio, may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG Instructions” on page 318. The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port.
ATmega16/32U4 25.7 25.7.1 On-chip Debug Related Register in I/O Memory On-chip Debug Register – OCDR Bit 7 6 5 4 3 2 1 0 MSB/IDRD LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 OCDR The OCDR Register provides a communication channel from the running program in the microcontroller to the debugger. The CPU can transfer a byte to the debugger by writing to this location.
ATmega16/32U4 26. IEEE 1149.1 (JTAG) Boundary-scan 26.1 Features • • • • • 26.2 JTAG (IEEE std. 1149.
ATmega16/32U4 26.3.1 Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested. 26.3.2 Device Identification Register Figure 26-1 shows the structure of the Device Identification Register. Figure 26-1.
ATmega16/32U4 Figure 26-2. Reset Register To TDO From Other Internal and External Reset Sources From TDI D Q Internal reset ClockDR · AVR_RESET 26.3.4 Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. See “Boundary-scan Chain” on page 324 for a complete description. 26.
ATmega16/32U4 The active states are: • Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain. • Shift-DR: The IDCODE scan chain is shifted by the TCK input. 26.4.3 SAMPLE_PRELOAD; 0x2 Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The Boundary-scan Chain is selected as Data Register.
ATmega16/32U4 26.5.2 MCU Status Register – MCUSR The MCU Status Register provides information on which reset source caused an MCU reset. Bit 7 6 5 4 3 2 1 0 – – – JTRF WDRF BORF EXTRF PORF Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 See Bit Description MCUSR • Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET.
ATmega16/32U4 Figure 26-3. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.
ATmega16/32U4 Figure 26-4. General Port Pin Schematic Diagram See Boundary-scan Description for Details! PUExn PUD Q D DDxn Q CLR RESET OCxn WDx Q Pxn ODxn D PORTxn Q CLR WRx IDxn DATA BUS RDx RESET RRx SLEEP SYNCHRONIZER D Q D RPx Q PINxn L Q Q CLK I/O PUD: PUExn: OCxn: ODxn: IDxn: SLEEP: 26.6.
ATmega16/32U4 26.7 ATmega16U4/ATmega32U4 Boundary-scan Order Table 26-3 shows the Scan order between TDI and TDO when the Boundary-scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Exceptions from the rules are the Scan chains for the analog circuits, which constitute the most significant bits of the scan chain regardless of which physical pin they are connected to.
ATmega16/32U4 Table 26-3. ATmega16U4/ATmega32U4 Boundary-scan Order (Continued) Bit Number Signal Name 61 PD0.Data 60 PD0.Control 59 PD1.Data 58 PD1.Control 57 PD2.Data 56 PD2.Control 55 PD3.Data 54 PD3.Control 53 PD4.Data 52 PD4.Control 51 PD5.Data 50 PD5.Control 49 PD6.Data 48 PD6.Control 47 PD7.Data 46 PD7.
ATmega16/32U4 Table 26-3. ATmega16U4/ATmega32U4 Boundary-scan Order (Continued) Bit Number Signal Name 25 PE2.Data 24 PE2.Control 23 Reserved 22 Reserved 21 Reserved 20 Reserved 19 Reserved 18 Reserved 17 Reserved 16 Reserved 15 Reserved 14 Reserved 13 Reserved 12 Reserved 11 Reserved 10 Reserved 9 Reserved 8 Reserved 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 PF1.Data 2 PF1.Control 1 PF0.Data 0 PF0.Control Module Port E Reserved Port F 26.
ATmega16/32U4 27. Boot Loader Support – Read-While-Write Self-Programming The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program.
ATmega16/32U4 sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-WhileWrite (NRWW) section. The limit between the RWW- and NRWW sections is given in Table 271 and Figure 27-1 on page 332. The main difference between the two sections is: • When erasing or writing a page located inside the RWW section, the NRWW section can be read during the operation.
ATmega16/32U4 Figure 27-1. Read-While-Write vs.
ATmega16/32U4 Figure 27-2.
ATmega16/32U4 Table 27-2. BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or (E)LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and (E)LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
ATmega16/32U4 is programmed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be changed through the serial or parallel programming interface. Table 27-4. BOOTRST Note: 27.5.3 Boot Reset Fuse(1) Reset Address 1 Reset Vector = Application Reset (address 0x0000) 0 Reset Vector = Boot Loader Reset (see Table 27-8 on page 344) 1.
ATmega16/32U4 27.5.4 Store Program Memory Control and Status Register – SPMCSR The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
ATmega16/32U4 • Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles.
ATmega16/32U4 Figure 27-4. Addressing the Flash During SPM(1) BIT 23 ZPCMSB ZPAGEMSB 1 0 0 PCMSB PROGRAM COUNTER Z - POINTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: 27.7 1. The different variables used in Figure 27-4 are listed in Table 27-10 on page 345. Self-Programming the Flash The program memory is updated in a page by page fashion.
ATmega16/32U4 page. See “Simple Assembly Code Example for a Boot Loader” on page 342 for an assembly code example. 27.7.1 Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation.
ATmega16/32U4 as described in “Interrupts” on page 61, or the interrupts must be disabled. Before addressing the RWW section after the programming is completed, the user software must clear the RWWSB by writing the RWWSRE. See “Simple Assembly Code Example for a Boot Loader” on page 342 for an example. 27.7.7 Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR.
ATmega16/32U4 Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an (E)LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below. Refer to Table 28-4 on page 348 for detailed description and mapping of the Fuse High byte.
ATmega16/32U4 1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock bits to prevent any Boot Loader software updates. 2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an external low VCC reset protection circuit can be used.
ATmega16/32U4 brne Wrloop ; execute Page Write subi ZL, low(PAGESIZEB) ;restore pointer sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256 ldi spmcrval, (1<
ATmega16/32U4 ATmega16U4/ATmega32U4 Boot Loader Parameters In Table 27-8 through Table 27-10, the parameters used in the description of the Self-Programming are given.
ATmega16/32U4 Table 27-10. Explanation of different variables used in Figure 27-4 and the mapping to the Zpointer Corresponding Z-value(1) Variable Description PCMSB 13 Most significant bit in the Program Counter. (The Program Counter is 14 bits PC[13:0]) PAGEMSB 6 Most significant bit which is used to address the words within one page (64 words in a page requires six bits PC [5:0]). ZPCMSB Z14 Bit in Z-pointer that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals PCMSB + 1.
ATmega16/32U4 28. Memory Programming 28.1 Program And Data Memory Lock Bits The ATmega16U4/ATmega32U4 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 28-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 28-1.
ATmega16/32U4 Lock Bit Protection Modes(1)(2) (Continued) Table 28-2. Memory Lock Bits Protection Type BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or (E)LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and (E)LPM executing from the Application section is not allowed to read from the Boot Loader section.
ATmega16/32U4 Table 28-4. Fuse High Byte Fuse High Byte Bit No Description Default Value OCDEN(4) 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN 6 Enable JTAG 0 (programmed, JTAG enabled) SPIEN(1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
ATmega16/32U4 28.2.1 28.3 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. Signature Bytes All ATMEL microcontrollers have a three-byte signature code which identifies the device.
ATmega16/32U4 Figure 28-1. Parallel Programming(1) +5V RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 XA1 PD6 PAGEL PD7 +12 V VCC +5V AVCC PB7 - PB0 DATA RESET BS2 PE6 XTAL1 GND Note: 1. Unused Pins should be left floating. Table 28-6. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O Function RDY/BSY PD1 O 0: Device is busy programming, 1: Device is ready for new command. OE PD2 I Output Enable (Active low). WR PD3 I Write Pulse (Active low).
ATmega16/32U4 , Table 28-8. Pin Values Used to Enter Programming Mode Pin Symbol Value PAGEL Prog_enable[3] 0 XA1 Prog_enable[2] 0 XA0 Prog_enable[1] 0 BS1 Prog_enable[0] 0 Table 28-9. XA1 and XA0 Enoding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS2 and BS1). 0 1 Load Data (High or Low data byte for Flash determined by BS1). 1 0 Load Command 1 1 No Action, Idle Table 28-10.
ATmega16/32U4 Table 28-12. No. of Words in a Page and No. of Pages in the EEPROM 28.6 28.6.1 EEPROM Size Page Size PCWORD No. of Pages PCPAGE EEAMSB 1K bytes 8 bytes EEA[2:0] 128 EEA[9:3] 9 Parallel Programming Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.5 - 5.5V between VCC and GND. 2. Set RESET to “0” and toggle XTAL1 at least six times. 3.
ATmega16/32U4 28.6.4 Programming the Flash The Flash is organized in pages, see Table 28-11 on page 351. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”. This is the command for Write Flash. 4.
ATmega16/32U4 3. Set DATA = Address extended high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address high byte. I. Program Page 1. Set BS2, BS1 to “00” 2. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 3. Wait until RDY/BSY goes high (See Figure 28-3 for signal waveforms). J. Repeat B through I until the entire Flash is programmed or until all data has been programmed. K. End Page Programming 1. 1. Set XA1, XA0 to “10”.
ATmega16/32U4 Figure 28-3. Programming the Flash Waveforms(1) F DATA A B C D E 0x10 ADDR. LOW DATA LOW DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G H ADDR. HIGH ADDR. EXT.H I XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL Note: 28.6.5 1. “XX” is don’t care. The letters refer to the programming description above. Programming the EEPROM The EEPROM is organized in pages, see Table 28-12 on page 352.
ATmega16/32U4 Figure 28-4. Programming the EEPROM Waveforms K DATA A G 0x11 ADDR. HIGH B ADDR. LOW C DATA E XX B ADDR. LOW C DATA E L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 28.6.6 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 353 for details on Command and Address loading): 1. A: Load Command “0000 0010”. 2. H: Load Address Extended Byte (0x00- 0xFF). 3. G: Load Address High Byte (0x00 - 0xFF).
ATmega16/32U4 28.6.9 Programming the Fuse High Bits The algorithm for programming the Fuse High bits is as follows (refer to “Programming the Flash” on page 353 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS2, BS1 to “01”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS2, BS1 to “00”. This selects low data byte. 28.6.
ATmega16/32U4 28.6.12 Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash” on page 353 for details on Command loading): 1. A: Load Command “0000 0100”. 2. Set OE to “0”, and BS2, BS1 to “00”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed). 3. Set OE to “0”, and BS2, BS1 to “11”. The status of the Fuse High bits can now be read at DATA (“0” means programmed). 4. Set OE to “0”, and BS2, BS1 to “10”.
ATmega16/32U4 28.6.15 Parallel Programming Characteristics Figure 28-7. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL XTAL1 tDVXH tXLDX Data & Contol (DATA, XA0/1, BS1, BS2) tPLBX t BVWL tBVPH PAGEL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 28-8.
ATmega16/32U4 Note: 1. The timing requirements shown in Figure 28-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 28-13. Parallel Programming Characteristics, VCC = 5V ± 10% Symbol Parameter Min VPP Programming Enable Voltage 11.
ATmega16/32U4 28.8 Serial Programming Pin Mapping Table 28-14. Pin Mapping Serial Programming Symbol Pins (TQFP-64) I/O Description PDI PB2 I Serial Data in PDO PB3 O Serial Data out SCK PB1 I Serial Clock Figure 28-10. Serial Programming and Verify(1) +1.8 - 5.5V VCC +1.8 - 5.5V(2) PDI AVCC PDO SCK XTAL1 RESET GND Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. 2. VCC - 0.3V < AVCC < VCC + 0.
ATmega16/32U4 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”. 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin PDI. 3.
ATmega16/32U4 Figure 28-11.
ATmega16/32U4 Table 28-16. Serial Programming Instruction Set Instruction Format Instruction Programming Enable Chip Erase Byte 1 Byte 2 Byte 3 Byte4 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. 0100 1101 0000 0000 cccc cccc xxxx xxxx Defines Extended Address Byte for Read Program Memory and Write Program Memory Page.
ATmega16/32U4 Table 28-16. Serial Programming Instruction Set (Continued) Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” = programmed, “1” = unprogrammed. See Table 28-3 on page 347 for details. 0011 1000 000x xxxx 0000 0000 oooo oooo Read Calibration Byte 1111 0000 0000 0000 xxxx xxxx xxxx xxxo If o = “1”, a programming operation is still busy.
ATmega16/32U4 Figure 28-12. State Machine Sequence for Changing the Instruction Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 28.9.
ATmega16/32U4 28.9.4 PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as Data Register. The active states are the following: • Capture-DR: The result of the previous command is loaded into the Data Register. • Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command.
ATmega16/32U4 28.9.8 Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering Programming mode. A high value in the Reset Register corresponds to pulling the external reset low. The part is reset as long as there is a high value present in the Reset Register.
ATmega16/32U4 Figure 28-14.
ATmega16/32U4 Table 28-17. JTAG Programming Instruction Set a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 1a. Chip Erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx 2a.
ATmega16/32U4 Table 28-17. JTAG Programming Instruction (Continued) Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 4g. Poll for Page Write Complete 0110011_00000000 xxxxxox_xxxxxxxx (2) 5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 5c.
ATmega16/32U4 Table 28-17. JTAG Programming Instruction (Continued) Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence 8d. Read Fuse Low Byte(8) 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 8e. Read Lock Bits(9) 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxoooooo (5) 8f.
ATmega16/32U4 Figure 28-15. State Machine Sequence for Changing/Reading the Data Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 Exit1-DR 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 28.9.
ATmega16/32U4 ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. Figure 28-16.
ATmega16/32U4 28.9.15 Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start Chip Erase using programming instruction 1a. 3. Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 28-13 on page 360). 28.9.16 Programming the Flash Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase” on page 375. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3.
ATmega16/32U4 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load the page address using programming instructions 3b, 3c and 3d. PCWORD (refer to Table 28-11 on page 351) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGEREAD. 5.
ATmega16/32U4 6. Load data low byte using programming instructions 6e. A “0” will program the fuse, a “1” will unprogram the fuse. 7. Write Fuse low byte using programming instruction 6f. 8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH (refer to Table 28-13 on page 360). 28.9.21 Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3. Load data using programming instructions 7b.
ATmega16/32U4 29. Electrical Characteristics 29.1 Absolute Maximum Ratings* Operating Temperature.................................... -40°C to +85°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET and VBUS with respect to Ground(8) .............................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.
ATmega16/32U4 TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Max.(5) Units 5 mA 15 mA Idle 4MHz, VCC = 3V (ATmega16U4/ATmega32U4) 2 mA Idle 8MHz, VCC = 5V (ATmega16U4/ATmega32U4) 6 mA <10 12 µA 1 5 µA <10 40 mV 50 nA Condition Min.(5) Typ.
ATmega16/32U4 7. Maximum regulator output current should be reduced by the USB buffer current required when USB is active (about 25mA). The remaining regulator output current can be used for the external application. 8. As specified on the USB Electrical chapter, the D+/D- pads can withstand voltages down to -1V applied through a 39 Ohms resistor 29.3 External Clock Drive Waveforms Figure 29-1. External Clock Drive Waveforms V IH1 V IL1 29.4 External Clock Drive Table 29-1. VCC=1.8-5.5V VCC=2.7-5.
ATmega16/32U4 Figure 29-2. Maximum Frequency vs. VCC, ATmega16U4/ATmega32U4 16 MHz 8 MHz Safe Operating Area 2.7V 29.6 4.5V 5.5V 2-wire Serial Interface Characteristics Table 29-2 describes the requirements for devices connected to the 2-wire Serial Bus. The ATmega16U4/ATmega32U4 2wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 29-3. Table 29-2.
ATmega16/32U4 Table 29-2. 2-wire Serial Bus Requirements (Continued) Symbol Parameter tHIGH High period of the SCL clock tSU;STA Set-up time for a repeated START condition tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition tBUF Bus free time between a STOP and START condition Notes: Condition Min Max Units fSCL ≤ 100 kHz 4.0 – µs fSCL > 100 kHz 0.6 – µs fSCL ≤ 100 kHz 4.7 – µs fSCL > 100 kHz 0.6 – µs fSCL ≤ 100 kHz 0 3.
ATmega16/32U4 29.7 SPI Timing Characteristics See Figure 29-4 and Figure 29-5 for details. Table 29-3. SPI Timing Parameters Description Mode 1 SCK period Master See Table 17-4 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master TBD 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
ATmega16/32U4 Figure 29-5. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) 29.8 17 MSB ... LSB X Hardware Boot EntranceTiming Characteristics Figure 29-6. Hardware Boot Timing Requirements RESET tSHRH tHHRH ALE/HWB Table 29-4. Symbol Parameter tSHRH HWB low Setup before Reset High tHHRH Table 29-5.
ATmega16/32U4 Table 29-5. Symbol INL DNL ADC Characteristics Parameter Integral Non-Linearity Differential Non-Linearity Gain Error Offset Error VREF Reference Voltage AVCC Analog Supply Voltage VIN Input Voltage Condition Min Typ Max VREF = 4V, VCC = 4V, ADC clock = 200 kHz 0.5 1.5 Gain = 1x/10x/40x, VREF = 4V, VCC = 5V, ADC clock = 200 kHz 0.3 1.5 Gain = 200x, VREF = 4V, VCC = 5V, ADC clock = 200 kHz 0.5 1.5 VREF = 4V, VCC = 4V, ADC clock = 200 kHz 0.4 0.
ATmega16/32U4 30. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR registers set and thus, the corresponding I/O modules are turned off.
ATmega16/32U4 Figure 30-2. Active Supply Current vs. Low Frequency (1MHz) and T= 85°C 2.3 5.5 V ICC (mA) 2.1 1.9 5.0 V 1.7 4.5 V 1.5 4.0 V 3.6 V 1.3 2.7 V 1.1 0.9 0.7 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-3. Active Supply Current vs. Frequency (1-16 MHz) and T= -40°C ICC (mA) 18 16 5.5V 14 5.0V 12 4.5V 10 4.0V 8 3.6V 6 2.
ATmega16/32U4 Figure 30-4. Active Supply Current vs. Frequency (1-16 MHz) and T = 25°C 16 5.5V 14 5.0V 12 4.5V ICC (mA) 10 4.0V 8 3.6V 6 4 2.7V 2 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 30-5. Active Supply Current vs. Frequency (1-16 MHz) and T = 85°C 16 5.5V 14 5.0V 12 4.5V ICC (mA) 10 4.0V 8 3.6V 6 4 2.
ATmega16/32U4 30.2 Idle Supply Current Figure 30-6. Idle Supply Current vs. Low Frequency (1 MHz) and T = 25°C ICC (mA) 0.5 0.45 5.5 V 0.4 5.0 V 0.35 4.5 V 0.3 4.0 V 3.6 V 0.25 0.2 2.7 V 0.15 0.1 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-7. Idle Supply Current vs. Low Frequency (1 MHz) and T = 85°C 0.5 5.5 V ICC (mA) 0.45 0.4 5.0 V 0.35 4.5 V 0.3 4.0 V 3.6 V 0.25 2.7 V 0.2 0.15 0.1 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
ATmega16/32U4 Figure 30-8. Idle Supply Current vs. Frequency (1-16 MHz) T = 25°C 7 5.5V 6 5.0V ICC (mA) 5 4.5V 4 4.0V 3 3.6V 2 3.3V 2.7V 1 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 30-9. Idle Supply Current vs. Frequency (1-16 MHz) T = 85°C 7 5.5V 6 5.0V ICC (mA) 5 4.5V 4 4.0V 3 3.6V 2 2.
ATmega16/32U4 30.3 Power-down Supply Current Figure 30-10. Power-Down Supply Current vs. VCC (WDT Disabled) 3.5 85 °C 3 ICC (uA) 2.5 2 1.5 1 25 °C -40 °C 0.5 0 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 30-11. Power-Down Supply Current vs. VCC (WDT Enabled) 24 85 °C 22 20 ICC (uA) 18 16 25 °C 14 12 -40 °C 10 8 6 4 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
ATmega16/32U4 Figure 30-12. Power-Down Supply Current vs. VCC (WDT Enabled, BOD EN) 48 85 °C 45 42 ICC (uA) 39 25 °C 36 -40 °C 33 30 27 24 21 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) 30.4 Power-save Supply Current Figure 30-13. Power-Save Supply Current vs. VCC (WDT Disabled ) 200 -40 °C 25 °C 85 °C 185 170 ICC (uA) 155 140 125 110 95 80 65 50 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
ATmega16/32U4 30.5 Pin Pull-Up Figure 30-14. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V) 80 70 60 IOP (uA) 50 40 30 20 25 °C -40 °C 85 °C 10 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 30-15. I/O Pin Pull-up Resistor Current vs.
ATmega16/32U4 Figure 30-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC=5V) 120 100 IRESET (uA) 80 60 40 25 °C 85 °C -40 °C 20 0 0 1 2 3 4 5 VRESET (V) 30.6 Pin Driver Strength Figure 30-17. I/O Pin Output Voltage vs. Sink Current (VCC = 3 V) 4 85 °C 3.5 3 VOL (V) 2.5 2 1.5 25 °C 1 -40 °C 0.
ATmega16/32U4 Figure 30-18. I/O Pin Output Voltage vs. Sink Current (VCC = 5 V) 1 85 °C 0.9 0.8 25 °C VOL (V) 0.7 0.6 -40 °C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 30-19. I/O Pin Output Voltage vs. Source Current (Vcc = 3 V) 3.5 3 VOH (V) 2.5 2 -40 °C 1.5 25 °C 1 0.
ATmega16/32U4 Figure 30-20. I/O Pin Output Voltage vs. Source Current (VCC = 5 V) 5.1 4.9 VOH (V) 4.7 4.5 -40 °C 4.3 25 °C 85 °C 4.1 3.9 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Figure 30-21. USB DP LO Pull-Up Resistor Current vs. USB Pin Voltage 2800 2400 IUSB (uA) 2000 1600 1200 800 85 °C 400 25 °C -40 °C 0 0 0.5 1 1.5 2 2.5 3 3.
ATmega16/32U4 30.7 Pin Threshold and Hysteresis Figure 30-22. I/O Pin Input Threshold Voltage vs. VCC (VIH, IO Pin read as ‘1’) 1.8 -40 °C 25 °C 85 °C Threshold (V) 1.6 1.4 1.2 1 0.8 0.6 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 30-23. I/O Pin Input Threshold Voltage vs. VCC (VIL, IO Pin read as ‘0’) 1.8 -40 °C 25 °C 85 °C Threshold (V) 1.6 1.4 1.2 1 0.8 0.6 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
ATmega16/32U4 Figure 30-24. USB Pin Input Threshold Voltage vs. VCC (VIH, IO Pin read as ‘1’) 2 85 °C 25 °C 1.9 Threshold (V) 1.8 -40 °C 1.7 1.6 1.5 1.4 1.3 1.2 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 VCC (V) Figure 30-25. USB Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) 1.6 -40 °C 85 °C 25 °C 1.5 Threshold (V) 1.4 1.3 1.2 1.1 1 0.9 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.
ATmega16/32U4 Figure 30-26. Vbus Pin Input Threshold Voltage vs. VCC (VIH, IO Pin read as ‘1’) 4.6 4.58 85 °C 4.56 25 °C Threshold (V) 4.54 4.52 4.5 4.48 4.46 4.44 4.42 4.4 -40 °C 4.38 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 30-27. Vbus Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) 1.52 85 °C 25 °C Threshold (V) 1.51 1.5 1.49 1.48 1.47 -40 °C 1.46 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
ATmega16/32U4 30.8 BOD Threshold Figure 30-28. BOD Thresholds vs. Temperature (BODLEVEL is 2.6 V) 2.8 Rising Vcc 2.78 Threshold (V) 2.76 2.74 Falling Vcc 2.72 2.7 2.68 2.66 2.64 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-29. BOD Thresholds vs. Temperature (BODLEVEL is 3.5 V) 3.73 Rising Vcc 3.69 Falling Vcc Threshold (V) 3.65 3.61 3.57 3.53 3.49 3.
ATmega16/32U4 Figure 30-30. BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V) 4.6 4.55 Falling Vcc Rising Vcc 4.5 Threshold (V) 4.45 4.4 4.35 4.3 4.25 4.2 4.15 4.1 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-31. Bandgap Voltage vs. Vcc 1.11 Bandgap Voltage (V) 1.1 1.09 85 °C 25 °C 1.08 1.07 1.06 -40 °C 1.05 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega16/32U4 Figure 30-32. Bandgap Voltage vs. Temperature 1.11 1.9 V 3.0 V 4.5 V 5.0 V 5.5 V Bandgap Voltage (V) 1.1 1.09 1.08 1.07 1.06 1.05 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) 30.9 Internal Oscilllator Speed Figure 30-33. Watchdog Oscillator Frequency vs. Temperature 124 122 FRC (kHz) 120 118 1.9 V 116 3.0 V 4.0 V 4.5 V 5.
ATmega16/32U4 Figure 30-34. Watchdog Oscillator Frequency vs. VCC 124 122 -40 °C FRC (kHz) 120 25 °C 118 116 114 85 °C 112 110 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-35. Calibrated 8 MHz RC Oscillator Frequency vs.
ATmega16/32U4 Figure 30-36. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature 8.4 2.7 V 4.0 V 5.5 V 8.3 FRC (MHz) 8.2 8.1 8 7.9 7.8 7.7 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-37. Calibrated 8 MHz RC Oscillator Frequency vs. Operating Voltage 8.4 8.3 85 °C FRC (MHz) 8.2 8.1 8 25 °C 7.9 7.8 -40 °C 7.7 7.6 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
ATmega16/32U4 Figure 30-38. OSCCAL VALUE STEP SIZE IN % (Base frequency = 0.0 MHz) 1.4 1.2 FRC change (%) 1 0.8 0.6 0.4 85 °C 0.2 -40 °C 25 °C 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) 30.10 Current Consumption of Peripheral Units Figure 30-39. USB Regulator Level vs. VCC 3.5 3.4 -40 °C 85 °C 3.3 25 °C ICC (uA) 3.2 3.1 3 2.9 2.8 2.7 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.
ATmega16/32U4 Figure 30-40. USB Regulator Level with load 75 Ω vs. VCC 3.4 -40 °C 85 °C 25 °C 3.3 3.2 Current (µA) 3.1 3 2.9 2.8 2.7 2.6 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 30-41. ADC Internal Vref vs. Vcc 2.54 2.53 Voltage VIntRef (V) 2.52 2.51 85 °C 25 °C 2.5 2.49 2.48 2.47 2.46 -40 °C 2.45 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5 5.3 5.
ATmega16/32U4 Figure 30-42. Internal Reference Voltage vs. Sink Current 2.52 85 °C 25 °C 2.51 Voltage VIntRef (V) 2.5 2.49 2.48 2.47 2.46 -40 °C 2.45 2.44 2.43 -7 -6 -5 -4 -3 -2 -1 0 Sink current (mA) 30.11 Current Consumption in Reset and Reset Pulsewidth Figure 30-43. Reset Supply Current vs. Frequency (1 - 20 MHz) ICC (mA) 3.5 5.5V 3 5.0V 2.5 4.5V 2 4.0V 3.6V 1.5 1 2.7V 0.
ATmega16/32U4 31.
ATmega16/32U4 Address Name (0xBE) TCNT4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page Timer/Counter4 - Counter Register Low Byte (0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 - (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE (0xBB) TWDR (0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE (0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 - TWPS1 TWPS0 (0xB8) TWBR (0xB7) Reserved - (0xB6) Reserved - (0xB5) Reserved (0xB4) Reserved (0x
ATmega16/32U4 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 (0x7B) ADCSRB ADHSM ACME MUX5 - ADTS3 ADTS2 ADTS1 ADTS0 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 (0x79) ADCH (0x78) ADCL (0x77) Reserved - - - - - - - - (0x76) Reserved - - - - - - - - (0x75) Reserved - - - - - - - - (0x74) Reserved - - - - - - - - (0x73) Reserved - - - - -
ATmega16/32U4 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x1B (0x3B) PCIFR - - - - - - - PCIF0 0x1A (0x3A) Reserved - - - - - - - - 0x19 (0x39) TIFR4 OCF4D OCF4A OCF4B - - TOV4 - - 0x18 (0x38) TIFR3 - - ICF3 - OCF3C OCF3B OCF3A TOV3 0x17 (0x37) Reserved - - - - - - - - 0x16 (0x36) TIFR1 - - ICF1 - OCF1C OCF1B OCF1A TOV1 0x15 (0x35) TIFR0 - - - - - OCF0B OCF0A TOV0 0x14 (0x34) Reserved - - - - - - - -
ATmega16/32U4 32.
ATmega16/32U4 Mnemonics Operands Description Operation Flags #Clocks BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n
ATmega16/32U4 Mnemonics Operands SPM IN Rd, P Description Operation Flags Store Program Memory (Z) ← R1:R0 None #Clocks - In Port Rd ← P None 1 1 OUT P, Rr Out Port P ← Rr None PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific description for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific description for WDR/timer) For On-c
ATmega16/32U4 33. Ordering Information 33.1 ATmega16U4 Speed (MHz) 16 Power Supply 2.7 - 5.5V Ordering Code Default Oscillator ATmega16U4-AU External XTAL ATmega16U4RC-AU Internal Calib. RC ATmega16U4-MU External XTAL ATmega16U4RC-MU Internal Calib. RC Package Operation Range 44ML Industrial (-40° to +85°C) 44PW Package Type 44ML ML, 44 - Lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 44PW PW, 44 - Lead 7.0 x 7.
ATmega16/32U4 33.2 ATmega32U4 Speed (MHz) 16 Power Supply 2.7 - 5.5 V Ordering Code Default Oscillator ATmega32U4-AU External XTAL ATmega32U4RC-AU Internal Calib. RC ATmega32U4-MU External XTAL ATmega32U4RC-MU Internal Calib. RC Package Operation Range 44ML Industrial (-40° to +85°C) 44PW Package Type 44ML ML, 44 - Lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 44PW PW, 44 - Lead 7.0 x 7.0 mm Body, 0.
ATmega16/32U4 34. Packaging Information 34.
ATmega16/32U4 34.
ATmega16/32U4 35. Errata The revision letter in this section refers to the revision of the ATmega16U4/ATmega32U4 device. 35.1 ATmega16U4/ATmega32U4 Rev E • Spike on TWI pins when TWI is enabled • High current consumption in sleep mode • MSB of OCR4A/B/D is write only in 11-bits enhanced PWM mode 1. Spike on TWI pins when TWI is enabled 100 ns negative spike occurs on SDA and SCL pins when TWI is enabled. Problem Fix/work around Enable ATmega16U4/ATmega32U4 TWI before the other nodes of the TWI network. 2.
ATmega16/32U4 3. Timer 4 11-bits enhanced PWM mode Timer 4 11-bits enhanced mode is not functional. Problem Fix/work around None. 35.3 ATmega16U4/ATmega32U4 Rev C Not sampled 35.4 ATmega16U4/ATmega32U4 Rev B • • • • Spike on TWI pins when TWI is enabled High current consumption in sleep mode Incorrect execution of VBUSTI interrupt Timer 4 11-bits enhanced PWM mode 1. Spike on TWI pins when TWI is enabled 100 ns negative spike occurs on SDA and SCL pins when TWI is enabled.
ATmega16/32U4 35.5 ATmega16U4/ATmega32U4 Rev A • • • • • • • Spike on TWI pins when TWI is enabled High current consumption in sleep mode Increased power consumption in power-down mode Internal RC oscillator start up may fail Internal RC oscillator calibration Incorrect execution of VBUSTI interrupt Timer 4 enhanced mode issue 1. Spike on TWI pins when TWI is enabled 100 ns negative spike occurs on SDA and SCL pins when TWI is enabled.
ATmega16/32U4 7. Timer 4 11-bits enhanced PWM mode Timer 4 11-bits enhanced mode is not functional. Problem Fix/work around None.
ATmega16/32U4 36. Datasheet Revision History for ATmega16U4/ATmega32U4 Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 36.1 36.2 36.3 36.4 Rev. 7766F – 11/10 1. Replaced the “QFN44” on page 418 by an updated drawing. 2. Updated “ADC Control and Status Register B – ADCSRB” on page 289. Defined the ADCSRB register as in “ADC Control and Status Register B – ADCSRB” on page 312. 3.
ATmega16/32U4 36.5 36.6 Rev. 7766B – 11/08 1. Added ATmega16U4 device. 2. Created errata section and added ATmega16U4. 3. Updated High Speed Timer, asynchronous description Section 15. on page 139 Rev. 7766A – 07/08 1.
ATmega16/32U4 Table of Contents 1 Pin Configurations ................................................................................... 3 2 Overview ................................................................................................... 3 2.1Block Diagram ...........................................................................................................4 2.2Pin Descriptions ........................................................................................................
6.10PLL ........................................................................................................................39 7 Power Management and Sleep Modes ................................................. 43 7.1Idle Mode .................................................................................................................44 7.2ADC Noise Reduction Mode ...................................................................................44 7.3Power-down Mode .............................
ATmega16/32U4 13.88-bit Timer/Counter Register Description ............................................................102 14 16-bit Timers/Counters (Timer/Counter1 and Timer/Counter3) ....... 108 14.1Overview .............................................................................................................108 14.2Accessing 16-bit Registers ..................................................................................110 14.3Timer/Counter Clock Sources .......................................
18.3Frame Formats ....................................................................................................190 18.4USART Initialization ............................................................................................192 18.5Data Transmission – The USART Transmitter ....................................................193 18.6Data Reception – The USART Receiver .............................................................195 18.7Asynchronous Data Reception ..............................
ATmega16/32U4 21.8Speed Control .....................................................................................................260 21.9Memory management .........................................................................................260 21.10PAD suspend ....................................................................................................261 21.11Plug-in detection ................................................................................................262 21.
24.8ADC Conversion Result ......................................................................................305 24.9ADC Register Description ...................................................................................307 25 JTAG Interface and On-chip Debug System ..................................... 314 25.1Overview .............................................................................................................314 25.2Test Access Port – TAP .........................................
ATmega16/32U4 28.6Parallel Programming ..........................................................................................352 28.7Serial Downloading .............................................................................................360 28.8Serial Programming Pin Mapping ........................................................................361 28.9Programming via the JTAG Interface ..................................................................365 29 Electrical Characteristics ........
35.1ATmega16U4/ATmega32U4 Rev E ....................................................................419 35.2ATmega16U4/ATmega32U4 Rev D ....................................................................419 35.3ATmega16U4/ATmega32U4 Rev C ....................................................................420 35.4ATmega16U4/ATmega32U4 Rev B ....................................................................420 35.5ATmega16U4/ATmega32U4 Rev A ................................................................
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg.
